xref: /openbmc/linux/Documentation/devicetree/bindings/sound/cs35l33.txt (revision 3eb66e91a25497065c5322b1268cbc3953642227)
1*7c2438c6SPaul HandriganCS35L33 Speaker Amplifier
2*7c2438c6SPaul Handrigan
3*7c2438c6SPaul HandriganRequired properties:
4*7c2438c6SPaul Handrigan
5*7c2438c6SPaul Handrigan  - compatible : "cirrus,cs35l33"
6*7c2438c6SPaul Handrigan
7*7c2438c6SPaul Handrigan  - reg : the I2C address of the device for I2C
8*7c2438c6SPaul Handrigan
9*7c2438c6SPaul Handrigan  - VA-supply, VP-supply : power supplies for the device,
10*7c2438c6SPaul Handrigan    as covered in
11*7c2438c6SPaul Handrigan    Documentation/devicetree/bindings/regulator/regulator.txt.
12*7c2438c6SPaul Handrigan
13*7c2438c6SPaul HandriganOptional properties:
14*7c2438c6SPaul Handrigan
15*7c2438c6SPaul Handrigan  - reset-gpios : gpio used to reset the amplifier
16*7c2438c6SPaul Handrigan
17*7c2438c6SPaul Handrigan -  interrupts : IRQ line info CS35L33.
18*7c2438c6SPaul Handrigan    (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
19*7c2438c6SPaul Handrigan    for further information relating to interrupt properties)
20*7c2438c6SPaul Handrigan
21*7c2438c6SPaul Handrigan  - cirrus,boost-ctl : Booster voltage use to supply the amp. If the value is
22*7c2438c6SPaul Handrigan    0, then VBST = VP. If greater than 0, the boost voltage will be 3300mV with
23*7c2438c6SPaul Handrigan    a value of 1 and will increase at a step size of 100mV until a maximum of
24*7c2438c6SPaul Handrigan    8000mV.
25*7c2438c6SPaul Handrigan
26*7c2438c6SPaul Handrigan  - cirrus,ramp-rate : On power up, it affects the time from when the power
27*7c2438c6SPaul Handrigan    up sequence begins to the time the audio reaches a full-scale output.
28*7c2438c6SPaul Handrigan    On power down, it affects the time from when the power-down sequence
29*7c2438c6SPaul Handrigan    begins to when the amplifier disables the PWM outputs. If this property
30*7c2438c6SPaul Handrigan    is not set then soft ramping will be disabled and ramp time would be
31*7c2438c6SPaul Handrigan    20ms. If this property is set to 0,1,2,3 then ramp times would be 40ms,
32*7c2438c6SPaul Handrigan    60ms,100ms,175ms respectively for 48KHz sample rate.
33*7c2438c6SPaul Handrigan
34*7c2438c6SPaul Handrigan  - cirrus,boost-ipk : The maximum current allowed for the boost converter.
35*7c2438c6SPaul Handrigan    The range starts at 1850000uA and goes to a maximum of 3600000uA
36*7c2438c6SPaul Handrigan    with a step size of 15625uA. The default is 2500000uA.
37*7c2438c6SPaul Handrigan
38*7c2438c6SPaul Handrigan  - cirrus,imon-adc-scale : Configures the scaling of data bits from the IMON
39*7c2438c6SPaul Handrigan    ADC data word. This property can be set as a value of 0 for bits 15 down
40*7c2438c6SPaul Handrigan    to 0, 6 for 21 down to 6, 7, for 22 down to 7, 8 for 23 down to 8.
41*7c2438c6SPaul Handrigan
42*7c2438c6SPaul Handrigan
43*7c2438c6SPaul HandriganOptional H/G Algorithm sub-node:
44*7c2438c6SPaul Handrigan
45*7c2438c6SPaul HandriganThe cs35l33 node can have a single "cirrus,hg-algo" sub-node that will enable
46*7c2438c6SPaul Handriganthe internal H/G Algorithm.
47*7c2438c6SPaul Handrigan
48*7c2438c6SPaul Handrigan  - cirrus,hg-algo : Sub-node for internal Class H/G algorithm that
49*7c2438c6SPaul Handrigan    controls the amplifier supplies.
50*7c2438c6SPaul Handrigan
51*7c2438c6SPaul HandriganOptional properties for the "cirrus,hg-algo" sub-node:
52*7c2438c6SPaul Handrigan
53*7c2438c6SPaul Handrigan  - cirrus,mem-depth : Memory depth for the Class H/G algorithm measured in
54*7c2438c6SPaul Handrigan    LRCLK cycles. If this property is set to 0, 1, 2, or 3 then the memory
55*7c2438c6SPaul Handrigan    depths will be 1, 4, 8, 16 LRCLK cycles.  The default is 16 LRCLK cycles.
56*7c2438c6SPaul Handrigan
57*7c2438c6SPaul Handrigan    cirrus,release-rate : The number of consecutive LRCLK periods before
58*7c2438c6SPaul Handrigan    allowing release condition tracking updates. The number of LRCLK periods
59*7c2438c6SPaul Handrigan    start at 3 to a maximum of 255.
60*7c2438c6SPaul Handrigan
61*7c2438c6SPaul Handrigan  - cirrus,ldo-thld : Configures the signal threshold at which the PWM output
62*7c2438c6SPaul Handrigan    stage enters LDO operation. Starts as a default value of 50mV for a value
63*7c2438c6SPaul Handrigan    of 1 and increases with a step size of 50mV to a maximum of 750mV (value of
64*7c2438c6SPaul Handrigan    0xF).
65*7c2438c6SPaul Handrigan
66*7c2438c6SPaul Handrigan  - cirrus,ldo-path-disable : This is a boolean property. If present, the H/G
67*7c2438c6SPaul Handrigan    algorithm uses the max detection path.  If not present, the LDO
68*7c2438c6SPaul Handrigan    detection path is used.
69*7c2438c6SPaul Handrigan
70*7c2438c6SPaul Handrigan  - cirrus,ldo-entry-delay : The LDO entry delay in milliseconds before the H/G
71*7c2438c6SPaul Handrigan    algorithm switches to the LDO voltage.  This property can be set to values
72*7c2438c6SPaul Handrigan    from 0 to 7 for delays of 5ms, 10ms, 50ms, 100ms, 200ms, 500ms, 1000ms.
73*7c2438c6SPaul Handrigan    The default is 100ms.
74*7c2438c6SPaul Handrigan
75*7c2438c6SPaul Handrigan  - cirrus,vp-hg-auto : This is a boolean property.  When set, class H/G VPhg
76*7c2438c6SPaul Handrigan    automatic updating is enabled.
77*7c2438c6SPaul Handrigan
78*7c2438c6SPaul Handrigan  - cirrus,vp-hg :  Class H/G algorithm VPhg.  Controls the H/G algorithm's
79*7c2438c6SPaul Handrigan    reference to the VP voltage for when to start generating a boosted VBST.
80*7c2438c6SPaul Handrigan    The reference voltage starts at 3000mV with a value of 0x3 and is increased
81*7c2438c6SPaul Handrigan    by 100mV per step to a maximum of 5500mV.
82*7c2438c6SPaul Handrigan
83*7c2438c6SPaul Handrigan  - cirrus,vp-hg-rate : The rate (number of LRCLK periods) at which the VPhg is
84*7c2438c6SPaul Handrigan    allowed to increase to a higher voltage when using VPhg automatic
85*7c2438c6SPaul Handrigan    tracking. This property can be set to values from 0 to 3 with rates of 128
86*7c2438c6SPaul Handrigan    periods, 2048 periods, 32768 periods, and 524288 periods.
87*7c2438c6SPaul Handrigan    The default is 32768 periods.
88*7c2438c6SPaul Handrigan
89*7c2438c6SPaul Handrigan  - cirrus,vp-hg-va : VA calculation reference for automatic VPhg tracking
90*7c2438c6SPaul Handrigan    using VPMON. This property can be set to values from 0 to 6 starting at
91*7c2438c6SPaul Handrigan    1800mV with a step size of 50mV up to a maximum value of 1750mV.
92*7c2438c6SPaul Handrigan    Default is 1800mV.
93*7c2438c6SPaul Handrigan
94*7c2438c6SPaul HandriganExample:
95*7c2438c6SPaul Handrigan
96*7c2438c6SPaul Handrigancs35l33: cs35l33@40 {
97*7c2438c6SPaul Handrigan	compatible = "cirrus,cs35l33";
98*7c2438c6SPaul Handrigan	reg = <0x40>;
99*7c2438c6SPaul Handrigan
100*7c2438c6SPaul Handrigan	VA-supply = <&ldo5_reg>;
101*7c2438c6SPaul Handrigan	VP-supply = <&ldo5_reg>;
102*7c2438c6SPaul Handrigan
103*7c2438c6SPaul Handrigan	interrupt-parent = <&gpio8>;
104*7c2438c6SPaul Handrigan	interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
105*7c2438c6SPaul Handrigan
106*7c2438c6SPaul Handrigan	reset-gpios = <&cs47l91 34 0>;
107*7c2438c6SPaul Handrigan
108*7c2438c6SPaul Handrigan	cirrus,ramp-rate = <0x0>;
109*7c2438c6SPaul Handrigan	cirrus,boost-ctl = <0x30>;  /* VBST = 8000mV */
110*7c2438c6SPaul Handrigan	cirrus,boost-ipk = <0xE0>; /* 3600mA */
111*7c2438c6SPaul Handrigan	cirrus,imon-adc-scale = <0> /* Bits 15 down to 0 */
112*7c2438c6SPaul Handrigan
113*7c2438c6SPaul Handrigan	cirrus,hg-algo {
114*7c2438c6SPaul Handrigan		cirrus,mem-depth = <0x3>;
115*7c2438c6SPaul Handrigan		cirrus,release-rate = <0x3>;
116*7c2438c6SPaul Handrigan		cirrus,ldo-thld = <0x1>;
117*7c2438c6SPaul Handrigan		cirrus,ldo-path-disable = <0x0>;
118*7c2438c6SPaul Handrigan		cirrus,ldo-entry-delay=<0x4>;
119*7c2438c6SPaul Handrigan		cirrus,vp-hg-auto;
120*7c2438c6SPaul Handrigan		cirrus,vp-hg=<0xF>;
121*7c2438c6SPaul Handrigan		cirrus,vp-hg-rate=<0x2>;
122*7c2438c6SPaul Handrigan		cirrus,vp-hg-va=<0x0>;
123*7c2438c6SPaul Handrigan	};
124*7c2438c6SPaul Handrigan};
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