1*d969f217SRoger Lu# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*d969f217SRoger Lu%YAML 1.2 3*d969f217SRoger Lu--- 4*d969f217SRoger Lu$id: http://devicetree.org/schemas/soc/mediatek/mtk-svs.yaml# 5*d969f217SRoger Lu$schema: http://devicetree.org/meta-schemas/core.yaml# 6*d969f217SRoger Lu 7*d969f217SRoger Lutitle: MediaTek Smart Voltage Scaling (SVS) Device Tree Bindings 8*d969f217SRoger Lu 9*d969f217SRoger Lumaintainers: 10*d969f217SRoger Lu - Roger Lu <roger.lu@mediatek.com> 11*d969f217SRoger Lu - Matthias Brugger <matthias.bgg@gmail.com> 12*d969f217SRoger Lu - Kevin Hilman <khilman@kernel.org> 13*d969f217SRoger Lu 14*d969f217SRoger Ludescription: |+ 15*d969f217SRoger Lu The SVS engine is a piece of hardware which has several 16*d969f217SRoger Lu controllers(banks) for calculating suitable voltage to 17*d969f217SRoger Lu different power domains(CPU/GPU/CCI) according to 18*d969f217SRoger Lu chip process corner, temperatures and other factors. Then DVFS 19*d969f217SRoger Lu driver could apply SVS bank voltage to PMIC/Buck. 20*d969f217SRoger Lu 21*d969f217SRoger Luproperties: 22*d969f217SRoger Lu compatible: 23*d969f217SRoger Lu enum: 24*d969f217SRoger Lu - mediatek,mt8183-svs 25*d969f217SRoger Lu 26*d969f217SRoger Lu reg: 27*d969f217SRoger Lu maxItems: 1 28*d969f217SRoger Lu description: Address range of the MTK SVS controller. 29*d969f217SRoger Lu 30*d969f217SRoger Lu interrupts: 31*d969f217SRoger Lu maxItems: 1 32*d969f217SRoger Lu 33*d969f217SRoger Lu clocks: 34*d969f217SRoger Lu maxItems: 1 35*d969f217SRoger Lu description: Main clock for MTK SVS controller to work. 36*d969f217SRoger Lu 37*d969f217SRoger Lu clock-names: 38*d969f217SRoger Lu const: main 39*d969f217SRoger Lu 40*d969f217SRoger Lu nvmem-cells: 41*d969f217SRoger Lu minItems: 1 42*d969f217SRoger Lu description: 43*d969f217SRoger Lu Phandle to the calibration data provided by a nvmem device. 44*d969f217SRoger Lu items: 45*d969f217SRoger Lu - description: SVS efuse for SVS controller 46*d969f217SRoger Lu - description: Thermal efuse for SVS controller 47*d969f217SRoger Lu 48*d969f217SRoger Lu nvmem-cell-names: 49*d969f217SRoger Lu items: 50*d969f217SRoger Lu - const: svs-calibration-data 51*d969f217SRoger Lu - const: t-calibration-data 52*d969f217SRoger Lu 53*d969f217SRoger Lurequired: 54*d969f217SRoger Lu - compatible 55*d969f217SRoger Lu - reg 56*d969f217SRoger Lu - interrupts 57*d969f217SRoger Lu - clocks 58*d969f217SRoger Lu - clock-names 59*d969f217SRoger Lu - nvmem-cells 60*d969f217SRoger Lu - nvmem-cell-names 61*d969f217SRoger Lu 62*d969f217SRoger LuadditionalProperties: false 63*d969f217SRoger Lu 64*d969f217SRoger Luexamples: 65*d969f217SRoger Lu - | 66*d969f217SRoger Lu #include <dt-bindings/clock/mt8183-clk.h> 67*d969f217SRoger Lu #include <dt-bindings/interrupt-controller/arm-gic.h> 68*d969f217SRoger Lu #include <dt-bindings/interrupt-controller/irq.h> 69*d969f217SRoger Lu 70*d969f217SRoger Lu soc { 71*d969f217SRoger Lu #address-cells = <2>; 72*d969f217SRoger Lu #size-cells = <2>; 73*d969f217SRoger Lu 74*d969f217SRoger Lu svs@1100b000 { 75*d969f217SRoger Lu compatible = "mediatek,mt8183-svs"; 76*d969f217SRoger Lu reg = <0 0x1100b000 0 0x1000>; 77*d969f217SRoger Lu interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 78*d969f217SRoger Lu clocks = <&infracfg CLK_INFRA_THERM>; 79*d969f217SRoger Lu clock-names = "main"; 80*d969f217SRoger Lu nvmem-cells = <&svs_calibration>, <&thermal_calibration>; 81*d969f217SRoger Lu nvmem-cell-names = "svs-calibration-data", "t-calibration-data"; 82*d969f217SRoger Lu }; 83*d969f217SRoger Lu }; 84