1*182c4e1fSLucas Stach# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*182c4e1fSLucas Stach%YAML 1.2 3*182c4e1fSLucas Stach--- 4*182c4e1fSLucas Stach$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml# 5*182c4e1fSLucas Stach$schema: http://devicetree.org/meta-schemas/core.yaml# 6*182c4e1fSLucas Stach 7*182c4e1fSLucas Stachtitle: NXP i.MX8MQ VPU blk-ctrl 8*182c4e1fSLucas Stach 9*182c4e1fSLucas Stachmaintainers: 10*182c4e1fSLucas Stach - Lucas Stach <l.stach@pengutronix.de> 11*182c4e1fSLucas Stach 12*182c4e1fSLucas Stachdescription: 13*182c4e1fSLucas Stach The i.MX8MQ VPU blk-ctrl is a top-level peripheral providing access to 14*182c4e1fSLucas Stach the NoC and ensuring proper power sequencing of the VPU peripherals 15*182c4e1fSLucas Stach located in the VPU domain of the SoC. 16*182c4e1fSLucas Stach 17*182c4e1fSLucas Stachproperties: 18*182c4e1fSLucas Stach compatible: 19*182c4e1fSLucas Stach items: 20*182c4e1fSLucas Stach - const: fsl,imx8mq-vpu-blk-ctrl 21*182c4e1fSLucas Stach 22*182c4e1fSLucas Stach reg: 23*182c4e1fSLucas Stach maxItems: 1 24*182c4e1fSLucas Stach 25*182c4e1fSLucas Stach '#power-domain-cells': 26*182c4e1fSLucas Stach const: 1 27*182c4e1fSLucas Stach 28*182c4e1fSLucas Stach power-domains: 29*182c4e1fSLucas Stach minItems: 3 30*182c4e1fSLucas Stach maxItems: 3 31*182c4e1fSLucas Stach 32*182c4e1fSLucas Stach power-domain-names: 33*182c4e1fSLucas Stach items: 34*182c4e1fSLucas Stach - const: bus 35*182c4e1fSLucas Stach - const: g1 36*182c4e1fSLucas Stach - const: g2 37*182c4e1fSLucas Stach 38*182c4e1fSLucas Stach clocks: 39*182c4e1fSLucas Stach minItems: 2 40*182c4e1fSLucas Stach maxItems: 2 41*182c4e1fSLucas Stach 42*182c4e1fSLucas Stach clock-names: 43*182c4e1fSLucas Stach items: 44*182c4e1fSLucas Stach - const: g1 45*182c4e1fSLucas Stach - const: g2 46*182c4e1fSLucas Stach 47*182c4e1fSLucas Stachrequired: 48*182c4e1fSLucas Stach - compatible 49*182c4e1fSLucas Stach - reg 50*182c4e1fSLucas Stach - power-domains 51*182c4e1fSLucas Stach - power-domain-names 52*182c4e1fSLucas Stach - clocks 53*182c4e1fSLucas Stach - clock-names 54*182c4e1fSLucas Stach 55*182c4e1fSLucas StachadditionalProperties: false 56*182c4e1fSLucas Stach 57*182c4e1fSLucas Stachexamples: 58*182c4e1fSLucas Stach - | 59*182c4e1fSLucas Stach #include <dt-bindings/clock/imx8mq-clock.h> 60*182c4e1fSLucas Stach #include <dt-bindings/power/imx8mq-power.h> 61*182c4e1fSLucas Stach 62*182c4e1fSLucas Stach vpu_blk_ctrl: blk-ctrl@38320000 { 63*182c4e1fSLucas Stach compatible = "fsl,imx8mq-vpu-blk-ctrl"; 64*182c4e1fSLucas Stach reg = <0x38320000 0x100>; 65*182c4e1fSLucas Stach power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; 66*182c4e1fSLucas Stach power-domain-names = "bus", "g1", "g2"; 67*182c4e1fSLucas Stach clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, 68*182c4e1fSLucas Stach <&clk IMX8MQ_CLK_VPU_G2_ROOT>; 69*182c4e1fSLucas Stach clock-names = "g1", "g2"; 70*182c4e1fSLucas Stach #power-domain-cells = <1>; 71*182c4e1fSLucas Stach }; 72