xref: /openbmc/linux/Documentation/devicetree/bindings/serial/8250.yaml (revision 3aa139aa9fdc138a84243dc49dc18d9b40e1c6e4) 
1# Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/serial/8250.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: UART (Universal Asynchronous Receiver/Transmitter) bindings
8
9maintainers:
10  - devicetree@vger.kernel.org
11
12allOf:
13  - $ref: /schemas/serial.yaml#
14  - if:
15      anyOf:
16        - required:
17            - aspeed,lpc-io-reg
18        - required:
19            - aspeed,lpc-interrupts
20        - required:
21            - aspeed,sirq-polarity-sense
22    then:
23      properties:
24        compatible:
25          const: aspeed,ast2500-vuart
26  - if:
27      properties:
28        compatible:
29          const: mrvl,mmp-uart
30    then:
31      properties:
32        reg-shift:
33          const: 2
34      required:
35        - reg-shift
36  - if:
37      not:
38        properties:
39          compatible:
40            items:
41              - enum:
42                  - ns8250
43                  - ns16450
44                  - ns16550
45                  - ns16550a
46    then:
47      anyOf:
48        - required: [ clock-frequency ]
49        - required: [ clocks ]
50
51properties:
52  compatible:
53    oneOf:
54      - const: ns8250
55      - const: ns16450
56      - const: ns16550
57      - const: ns16550a
58      - const: ns16850
59      - const: aspeed,ast2400-vuart
60      - const: aspeed,ast2500-vuart
61      - const: intel,xscale-uart
62      - const: mrvl,pxa-uart
63      - const: nuvoton,wpcm450-uart
64      - const: nuvoton,npcm750-uart
65      - const: nvidia,tegra20-uart
66      - const: nxp,lpc3220-uart
67      - items:
68          - enum:
69              - altr,16550-FIFO32
70              - altr,16550-FIFO64
71              - altr,16550-FIFO128
72              - fsl,16550-FIFO64
73              - fsl,ns16550
74              - andestech,uart16550
75              - nxp,lpc1850-uart
76              - opencores,uart16550-rtlsvn105
77              - ti,da830-uart
78          - const: ns16550a
79      - items:
80          - enum:
81              - ns16750
82              - cavium,octeon-3860-uart
83              - xlnx,xps-uart16550-2.00.b
84              - ralink,rt2880-uart
85          - enum:
86              - ns16550 # Deprecated, unless the FIFO really is broken
87              - ns16550a
88      - items:
89          - enum:
90              - ralink,mt7620a-uart
91              - ralink,rt3052-uart
92              - ralink,rt3883-uart
93          - const: ralink,rt2880-uart
94          - enum:
95              - ns16550 # Deprecated, unless the FIFO really is broken
96              - ns16550a
97      - items:
98          - enum:
99              - mediatek,mt7622-btif
100              - mediatek,mt7623-btif
101          - const: mediatek,mtk-btif
102      - items:
103          - enum:
104              - mediatek,mt7622-btif
105              - mediatek,mt7623-btif
106          - const: mediatek,mtk-btif
107      - items:
108          - const: mrvl,mmp-uart
109          - const: intel,xscale-uart
110      - items:
111          - enum:
112              - nvidia,tegra30-uart
113              - nvidia,tegra114-uart
114              - nvidia,tegra124-uart
115              - nvidia,tegra186-uart
116              - nvidia,tegra194-uart
117              - nvidia,tegra210-uart
118          - const: nvidia,tegra20-uart
119
120  reg:
121    maxItems: 1
122
123  interrupts:
124    maxItems: 1
125
126  clock-frequency: true
127
128  clocks:
129    maxItems: 1
130
131  resets:
132    maxItems: 1
133
134  current-speed:
135    $ref: /schemas/types.yaml#/definitions/uint32
136    description: The current active speed of the UART.
137
138  reg-offset:
139    description: |
140      Offset to apply to the mapbase from the start of the registers.
141
142  reg-shift:
143    description: Quantity to shift the register offsets by.
144
145  reg-io-width:
146    description: |
147      The size (in bytes) of the IO accesses that should be performed on the
148      device. There are some systems that require 32-bit accesses to the
149      UART (e.g. TI davinci).
150
151  used-by-rtas:
152    type: boolean
153    description: |
154      Set to indicate that the port is in use by the OpenFirmware RTAS and
155      should not be registered.
156
157  no-loopback-test:
158    type: boolean
159    description: |
160      Set to indicate that the port does not implement loopback test mode.
161
162  fifo-size:
163    $ref: /schemas/types.yaml#/definitions/uint32
164    description: The fifo size of the UART.
165
166  auto-flow-control:
167    type: boolean
168    description: |
169      One way to enable automatic flow control support. The driver is
170      allowed to detect support for the capability even without this
171      property.
172
173  tx-threshold:
174    description: |
175      Specify the TX FIFO low water indication for parts with programmable
176      TX FIFO thresholds.
177
178  overrun-throttle-ms:
179    description: |
180      How long to pause uart rx when input overrun is encountered.
181
182  rts-gpios: true
183  cts-gpios: true
184  dtr-gpios: true
185  dsr-gpios: true
186  rng-gpios: true
187  dcd-gpios: true
188
189  aspeed,sirq-polarity-sense:
190    $ref: /schemas/types.yaml#/definitions/phandle-array
191    description: |
192      Phandle to aspeed,ast2500-scu compatible syscon alongside register
193      offset and bit number to identify how the SIRQ polarity should be
194      configured. One possible data source is the LPC/eSPI mode bit. Only
195      applicable to aspeed,ast2500-vuart.
196    deprecated: true
197
198  aspeed,lpc-io-reg:
199    $ref: '/schemas/types.yaml#/definitions/uint32'
200    description: |
201      The VUART LPC address.  Only applicable to aspeed,ast2500-vuart.
202
203  aspeed,lpc-interrupts:
204    $ref: "/schemas/types.yaml#/definitions/uint32-array"
205    minItems: 2
206    maxItems: 2
207    description: |
208      A 2-cell property describing the VUART SIRQ number and SIRQ
209      polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH).  Only
210      applicable to aspeed,ast2500-vuart.
211
212required:
213  - reg
214  - interrupts
215
216unevaluatedProperties: false
217
218examples:
219  - |
220    serial@80230000 {
221        compatible = "ns8250";
222        reg = <0x80230000 0x100>;
223        interrupts = <10>;
224        reg-shift = <2>;
225        clock-frequency = <48000000>;
226    };
227  - |
228    #include <dt-bindings/gpio/gpio.h>
229    serial@49042000 {
230        compatible = "andestech,uart16550", "ns16550a";
231        reg = <0x49042000 0x400>;
232        interrupts = <80>;
233        clock-frequency = <48000000>;
234        cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
235        rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
236        dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
237        dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
238        dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
239        rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
240    };
241  - |
242    #include <dt-bindings/clock/aspeed-clock.h>
243    #include <dt-bindings/interrupt-controller/irq.h>
244    serial@1e787000 {
245        compatible = "aspeed,ast2500-vuart";
246        reg = <0x1e787000 0x40>;
247        reg-shift = <2>;
248        interrupts = <8>;
249        clocks = <&syscon ASPEED_CLK_APB>;
250        no-loopback-test;
251        aspeed,lpc-io-reg = <0x3f8>;
252        aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
253    };
254
255...
256