1*5059791eSBenjamin Gaignard# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*5059791eSBenjamin Gaignard%YAML 1.2 3*5059791eSBenjamin Gaignard--- 4*5059791eSBenjamin Gaignard$id: http://devicetree.org/schemas/rng/st,stm32-rng.yaml# 5*5059791eSBenjamin Gaignard$schema: http://devicetree.org/meta-schemas/core.yaml# 6*5059791eSBenjamin Gaignard 7*5059791eSBenjamin Gaignardtitle: STMicroelectronics STM32 RNG bindings 8*5059791eSBenjamin Gaignard 9*5059791eSBenjamin Gaignarddescription: | 10*5059791eSBenjamin Gaignard The STM32 hardware random number generator is a simple fixed purpose 11*5059791eSBenjamin Gaignard IP and is fully separated from other crypto functions. 12*5059791eSBenjamin Gaignard 13*5059791eSBenjamin Gaignardmaintainers: 14*5059791eSBenjamin Gaignard - Lionel Debieve <lionel.debieve@st.com> 15*5059791eSBenjamin Gaignard 16*5059791eSBenjamin Gaignardproperties: 17*5059791eSBenjamin Gaignard compatible: 18*5059791eSBenjamin Gaignard const: st,stm32-rng 19*5059791eSBenjamin Gaignard 20*5059791eSBenjamin Gaignard reg: 21*5059791eSBenjamin Gaignard maxItems: 1 22*5059791eSBenjamin Gaignard 23*5059791eSBenjamin Gaignard clocks: 24*5059791eSBenjamin Gaignard maxItems: 1 25*5059791eSBenjamin Gaignard 26*5059791eSBenjamin Gaignard resets: 27*5059791eSBenjamin Gaignard maxItems: 1 28*5059791eSBenjamin Gaignard 29*5059791eSBenjamin Gaignard clock-error-detect: 30*5059791eSBenjamin Gaignard description: If set enable the clock detection management 31*5059791eSBenjamin Gaignard 32*5059791eSBenjamin Gaignardrequired: 33*5059791eSBenjamin Gaignard - compatible 34*5059791eSBenjamin Gaignard - reg 35*5059791eSBenjamin Gaignard - clocks 36*5059791eSBenjamin Gaignard 37*5059791eSBenjamin GaignardadditionalProperties: false 38*5059791eSBenjamin Gaignard 39*5059791eSBenjamin Gaignardexamples: 40*5059791eSBenjamin Gaignard - | 41*5059791eSBenjamin Gaignard #include <dt-bindings/clock/stm32mp1-clks.h> 42*5059791eSBenjamin Gaignard rng@54003000 { 43*5059791eSBenjamin Gaignard compatible = "st,stm32-rng"; 44*5059791eSBenjamin Gaignard reg = <0x54003000 0x400>; 45*5059791eSBenjamin Gaignard clocks = <&rcc RNG1_K>; 46*5059791eSBenjamin Gaignard }; 47*5059791eSBenjamin Gaignard 48*5059791eSBenjamin Gaignard... 49