1*003910ebSNishanth Menon* Pin configuration for TI IODELAY controller 2*003910ebSNishanth Menon 3*003910ebSNishanth MenonTI dra7 based SoCs such as am57xx have a controller for setting the IO delay 4*003910ebSNishanth Menonfor each pin. For most part the IO delay values are programmed by the bootloader, 5*003910ebSNishanth Menonbut some pins need to be configured dynamically by the kernel such as the 6*003910ebSNishanth MenonMMC pins. 7*003910ebSNishanth Menon 8*003910ebSNishanth MenonRequired Properties: 9*003910ebSNishanth Menon 10*003910ebSNishanth Menon - compatible: Must be "ti,dra7-iodelay" 11*003910ebSNishanth Menon - reg: Base address and length of the memory resource used 12*003910ebSNishanth Menon - #address-cells: Number of address cells 13*003910ebSNishanth Menon - #size-cells: Size of cells 14*003910ebSNishanth Menon - #pinctrl-cells: Number of pinctrl cells, must be 2. See also 15*003910ebSNishanth Menon Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt 16*003910ebSNishanth Menon 17*003910ebSNishanth MenonExample 18*003910ebSNishanth Menon------- 19*003910ebSNishanth Menon 20*003910ebSNishanth MenonIn the SoC specific dtsi file: 21*003910ebSNishanth Menon 22*003910ebSNishanth Menon dra7_iodelay_core: padconf@4844a000 { 23*003910ebSNishanth Menon compatible = "ti,dra7-iodelay"; 24*003910ebSNishanth Menon reg = <0x4844a000 0x0d1c>; 25*003910ebSNishanth Menon #address-cells = <1>; 26*003910ebSNishanth Menon #size-cells = <0>; 27*003910ebSNishanth Menon #pinctrl-cells = <2>; 28*003910ebSNishanth Menon }; 29*003910ebSNishanth Menon 30*003910ebSNishanth MenonIn board-specific file: 31*003910ebSNishanth Menon 32*003910ebSNishanth Menon&dra7_iodelay_core { 33*003910ebSNishanth Menon mmc2_iodelay_3v3_conf: mmc2_iodelay_3v3_conf { 34*003910ebSNishanth Menon pinctrl-pin-array = < 35*003910ebSNishanth Menon 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */ 36*003910ebSNishanth Menon 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */ 37*003910ebSNishanth Menon 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */ 38*003910ebSNishanth Menon 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */ 39*003910ebSNishanth Menon 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */ 40*003910ebSNishanth Menon 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */ 41*003910ebSNishanth Menon 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ 42*003910ebSNishanth Menon 0x1ec A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */ 43*003910ebSNishanth Menon 0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */ 44*003910ebSNishanth Menon 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ 45*003910ebSNishanth Menon >; 46*003910ebSNishanth Menon }; 47*003910ebSNishanth Menon}; 48