1*d6e0a660SJianlong Huang# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2*d6e0a660SJianlong Huang%YAML 1.2 3*d6e0a660SJianlong Huang--- 4*d6e0a660SJianlong Huang$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-sys-pinctrl.yaml# 5*d6e0a660SJianlong Huang$schema: http://devicetree.org/meta-schemas/core.yaml# 6*d6e0a660SJianlong Huang 7*d6e0a660SJianlong Huangtitle: StarFive JH7110 SYS Pin Controller 8*d6e0a660SJianlong Huang 9*d6e0a660SJianlong Huangdescription: | 10*d6e0a660SJianlong Huang Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd. 11*d6e0a660SJianlong Huang 12*d6e0a660SJianlong Huang Out of the SoC's many pins only the ones named PAD_GPIO0 to PAD_GPIO63 13*d6e0a660SJianlong Huang can be multiplexed and have configurable bias, drive strength, 14*d6e0a660SJianlong Huang schmitt trigger etc. 15*d6e0a660SJianlong Huang Some peripherals have their I/O go through the 64 "GPIOs". This also 16*d6e0a660SJianlong Huang includes a number of other UARTs, I2Cs, SPIs, PWMs etc. 17*d6e0a660SJianlong Huang All these peripherals are connected to all 64 GPIOs such that 18*d6e0a660SJianlong Huang any GPIO can be set up to be controlled by any of the peripherals. 19*d6e0a660SJianlong Huang 20*d6e0a660SJianlong Huangmaintainers: 21*d6e0a660SJianlong Huang - Jianlong Huang <jianlong.huang@starfivetech.com> 22*d6e0a660SJianlong Huang 23*d6e0a660SJianlong Huangproperties: 24*d6e0a660SJianlong Huang compatible: 25*d6e0a660SJianlong Huang const: starfive,jh7110-sys-pinctrl 26*d6e0a660SJianlong Huang 27*d6e0a660SJianlong Huang reg: 28*d6e0a660SJianlong Huang maxItems: 1 29*d6e0a660SJianlong Huang 30*d6e0a660SJianlong Huang clocks: 31*d6e0a660SJianlong Huang maxItems: 1 32*d6e0a660SJianlong Huang 33*d6e0a660SJianlong Huang resets: 34*d6e0a660SJianlong Huang maxItems: 1 35*d6e0a660SJianlong Huang 36*d6e0a660SJianlong Huang interrupts: 37*d6e0a660SJianlong Huang maxItems: 1 38*d6e0a660SJianlong Huang 39*d6e0a660SJianlong Huang interrupt-controller: true 40*d6e0a660SJianlong Huang 41*d6e0a660SJianlong Huang '#interrupt-cells': 42*d6e0a660SJianlong Huang const: 2 43*d6e0a660SJianlong Huang 44*d6e0a660SJianlong Huang gpio-controller: true 45*d6e0a660SJianlong Huang 46*d6e0a660SJianlong Huang '#gpio-cells': 47*d6e0a660SJianlong Huang const: 2 48*d6e0a660SJianlong Huang 49*d6e0a660SJianlong HuangpatternProperties: 50*d6e0a660SJianlong Huang '-[0-9]+$': 51*d6e0a660SJianlong Huang type: object 52*d6e0a660SJianlong Huang additionalProperties: false 53*d6e0a660SJianlong Huang patternProperties: 54*d6e0a660SJianlong Huang '-pins$': 55*d6e0a660SJianlong Huang type: object 56*d6e0a660SJianlong Huang description: | 57*d6e0a660SJianlong Huang A pinctrl node should contain at least one subnode representing the 58*d6e0a660SJianlong Huang pinctrl groups available on the machine. Each subnode will list the 59*d6e0a660SJianlong Huang pins it needs, and how they should be configured, with regard to 60*d6e0a660SJianlong Huang muxer configuration, bias, input enable/disable, input schmitt 61*d6e0a660SJianlong Huang trigger enable/disable, slew-rate and drive strength. 62*d6e0a660SJianlong Huang allOf: 63*d6e0a660SJianlong Huang - $ref: /schemas/pinctrl/pincfg-node.yaml 64*d6e0a660SJianlong Huang - $ref: /schemas/pinctrl/pinmux-node.yaml 65*d6e0a660SJianlong Huang additionalProperties: false 66*d6e0a660SJianlong Huang 67*d6e0a660SJianlong Huang properties: 68*d6e0a660SJianlong Huang pinmux: 69*d6e0a660SJianlong Huang description: | 70*d6e0a660SJianlong Huang The list of GPIOs and their mux settings that properties in the 71*d6e0a660SJianlong Huang node apply to. This should be set using the GPIOMUX or PINMUX 72*d6e0a660SJianlong Huang macros. 73*d6e0a660SJianlong Huang 74*d6e0a660SJianlong Huang bias-disable: true 75*d6e0a660SJianlong Huang 76*d6e0a660SJianlong Huang bias-pull-up: 77*d6e0a660SJianlong Huang type: boolean 78*d6e0a660SJianlong Huang 79*d6e0a660SJianlong Huang bias-pull-down: 80*d6e0a660SJianlong Huang type: boolean 81*d6e0a660SJianlong Huang 82*d6e0a660SJianlong Huang drive-strength: 83*d6e0a660SJianlong Huang enum: [ 2, 4, 8, 12 ] 84*d6e0a660SJianlong Huang 85*d6e0a660SJianlong Huang input-enable: true 86*d6e0a660SJianlong Huang 87*d6e0a660SJianlong Huang input-disable: true 88*d6e0a660SJianlong Huang 89*d6e0a660SJianlong Huang input-schmitt-enable: true 90*d6e0a660SJianlong Huang 91*d6e0a660SJianlong Huang input-schmitt-disable: true 92*d6e0a660SJianlong Huang 93*d6e0a660SJianlong Huang slew-rate: 94*d6e0a660SJianlong Huang maximum: 1 95*d6e0a660SJianlong Huang 96*d6e0a660SJianlong Huangrequired: 97*d6e0a660SJianlong Huang - compatible 98*d6e0a660SJianlong Huang - reg 99*d6e0a660SJianlong Huang - clocks 100*d6e0a660SJianlong Huang - interrupts 101*d6e0a660SJianlong Huang - interrupt-controller 102*d6e0a660SJianlong Huang - '#interrupt-cells' 103*d6e0a660SJianlong Huang - gpio-controller 104*d6e0a660SJianlong Huang - '#gpio-cells' 105*d6e0a660SJianlong Huang 106*d6e0a660SJianlong HuangadditionalProperties: false 107*d6e0a660SJianlong Huang 108*d6e0a660SJianlong Huangexamples: 109*d6e0a660SJianlong Huang - | 110*d6e0a660SJianlong Huang pinctrl@13040000 { 111*d6e0a660SJianlong Huang compatible = "starfive,jh7110-sys-pinctrl"; 112*d6e0a660SJianlong Huang reg = <0x13040000 0x10000>; 113*d6e0a660SJianlong Huang clocks = <&syscrg 112>; 114*d6e0a660SJianlong Huang resets = <&syscrg 2>; 115*d6e0a660SJianlong Huang interrupts = <86>; 116*d6e0a660SJianlong Huang interrupt-controller; 117*d6e0a660SJianlong Huang #interrupt-cells = <2>; 118*d6e0a660SJianlong Huang gpio-controller; 119*d6e0a660SJianlong Huang #gpio-cells = <2>; 120*d6e0a660SJianlong Huang 121*d6e0a660SJianlong Huang uart0-0 { 122*d6e0a660SJianlong Huang tx-pins { 123*d6e0a660SJianlong Huang pinmux = <0xff140005>; 124*d6e0a660SJianlong Huang bias-disable; 125*d6e0a660SJianlong Huang drive-strength = <12>; 126*d6e0a660SJianlong Huang input-disable; 127*d6e0a660SJianlong Huang input-schmitt-disable; 128*d6e0a660SJianlong Huang slew-rate = <0>; 129*d6e0a660SJianlong Huang }; 130*d6e0a660SJianlong Huang 131*d6e0a660SJianlong Huang rx-pins { 132*d6e0a660SJianlong Huang pinmux = <0x0E000406>; 133*d6e0a660SJianlong Huang bias-pull-up; 134*d6e0a660SJianlong Huang drive-strength = <2>; 135*d6e0a660SJianlong Huang input-enable; 136*d6e0a660SJianlong Huang input-schmitt-enable; 137*d6e0a660SJianlong Huang slew-rate = <0>; 138*d6e0a660SJianlong Huang }; 139*d6e0a660SJianlong Huang }; 140*d6e0a660SJianlong Huang }; 141*d6e0a660SJianlong Huang 142*d6e0a660SJianlong Huang... 143