xref: /openbmc/linux/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml (revision c900529f3d9161bfde5cca0754f83b4d3c3e0220)
165916a1cSSam Shih# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
265916a1cSSam Shih%YAML 1.2
365916a1cSSam Shih---
465916a1cSSam Shih$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7986-pinctrl.yaml#
565916a1cSSam Shih$schema: http://devicetree.org/meta-schemas/core.yaml#
665916a1cSSam Shih
7a9d44c4cSArınç ÜNALtitle: MediaTek MT7986 Pin Controller
865916a1cSSam Shih
965916a1cSSam Shihmaintainers:
1065916a1cSSam Shih  - Sean Wang <sean.wang@kernel.org>
1165916a1cSSam Shih
12c911ad22SArınç ÜNALdescription:
1365916a1cSSam Shih  The MediaTek's MT7986 Pin controller is used to control SoC pins.
1465916a1cSSam Shih
1565916a1cSSam Shihproperties:
1665916a1cSSam Shih  compatible:
1765916a1cSSam Shih    enum:
1865916a1cSSam Shih      - mediatek,mt7986a-pinctrl
1965916a1cSSam Shih      - mediatek,mt7986b-pinctrl
2065916a1cSSam Shih
2165916a1cSSam Shih  reg:
2265916a1cSSam Shih    minItems: 8
2365916a1cSSam Shih    maxItems: 8
2465916a1cSSam Shih
2565916a1cSSam Shih  reg-names:
2665916a1cSSam Shih    items:
2765916a1cSSam Shih      - const: gpio
2865916a1cSSam Shih      - const: iocfg_rt
2965916a1cSSam Shih      - const: iocfg_rb
3065916a1cSSam Shih      - const: iocfg_lt
3165916a1cSSam Shih      - const: iocfg_lb
3265916a1cSSam Shih      - const: iocfg_tr
3365916a1cSSam Shih      - const: iocfg_tl
3465916a1cSSam Shih      - const: eint
3565916a1cSSam Shih
3665916a1cSSam Shih  gpio-controller: true
3765916a1cSSam Shih
3865916a1cSSam Shih  "#gpio-cells":
3965916a1cSSam Shih    const: 2
40c911ad22SArınç ÜNAL    description:
41c911ad22SArınç ÜNAL      Number of cells in GPIO specifier. Since the generic GPIO binding is used,
42c911ad22SArınç ÜNAL      the amount of cells must be specified as 2. See the below mentioned gpio
43c911ad22SArınç ÜNAL      binding representation for description of particular cells.
4465916a1cSSam Shih
4565916a1cSSam Shih  gpio-ranges:
4665916a1cSSam Shih    minItems: 1
4765916a1cSSam Shih    maxItems: 5
48c911ad22SArınç ÜNAL    description:
4965916a1cSSam Shih      GPIO valid number range.
5065916a1cSSam Shih
5165916a1cSSam Shih  interrupt-controller: true
5265916a1cSSam Shih
5365916a1cSSam Shih  interrupts:
5465916a1cSSam Shih    maxItems: 1
5565916a1cSSam Shih
5665916a1cSSam Shih  "#interrupt-cells":
5765916a1cSSam Shih    const: 2
5865916a1cSSam Shih
59c09acbc4SRafał MiłeckiallOf:
606a735ad5SArınç ÜNAL  - $ref: pinctrl.yaml#
61c09acbc4SRafał Miłecki
6265916a1cSSam Shihrequired:
6365916a1cSSam Shih  - compatible
6465916a1cSSam Shih  - reg
6565916a1cSSam Shih  - reg-names
6665916a1cSSam Shih  - gpio-controller
6765916a1cSSam Shih  - "#gpio-cells"
6865916a1cSSam Shih
6965916a1cSSam ShihpatternProperties:
7065916a1cSSam Shih  '-pins$':
7165916a1cSSam Shih    type: object
7265916a1cSSam Shih    additionalProperties: false
7365916a1cSSam Shih
7465916a1cSSam Shih    patternProperties:
754b8efbaeSArınç ÜNAL      '^.*mux.*$':
7665916a1cSSam Shih        type: object
7765916a1cSSam Shih        additionalProperties: false
7865916a1cSSam Shih        description: |
7965916a1cSSam Shih          pinmux configuration nodes.
8065916a1cSSam Shih
8165916a1cSSam Shih          The following table shows the effective values of "group", "function"
8265916a1cSSam Shih          properties and chip pinout pins
8365916a1cSSam Shih
8465916a1cSSam Shih          groups            function    pins (in pin#)
8565916a1cSSam Shih          ---------------------------------------------------------------------
8665916a1cSSam Shih          "watchdog"        "watchdog"  0
8765916a1cSSam Shih          "wifi_led"        "led"       1, 2
8865916a1cSSam Shih          "i2c"             "i2c"       3, 4
8965916a1cSSam Shih          "uart1_0"         "uart"      7, 8, 9, 10
90c115e7f5SFrank Wunderlich          "uart1_rx_tx"     "uart"      42, 43
91c115e7f5SFrank Wunderlich          "uart1_cts_rts"   "uart"      44, 45
9265916a1cSSam Shih          "pcie_clk"        "pcie"      9
9365916a1cSSam Shih          "pcie_wake"       "pcie"      10
9465916a1cSSam Shih          "spi1_0"          "spi"       11, 12, 13, 14
9565916a1cSSam Shih          "pwm1_1"          "pwm"       20,
9665916a1cSSam Shih          "pwm0"            "pwm"       21,
9765916a1cSSam Shih          "pwm1_0"          "pwm"       22,
9865916a1cSSam Shih          "snfi"            "flash"     23, 24, 25, 26, 27, 28
9965916a1cSSam Shih          "spi1_2"          "spi"       29, 30, 31, 32
100c911ad22SArınç ÜNAL          "emmc_45"         "emmc"      22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
101c911ad22SArınç ÜNAL                                        32
102c911ad22SArınç ÜNAL
10365916a1cSSam Shih          "spi1_1"          "spi"       23, 24, 25, 26
104c115e7f5SFrank Wunderlich          "uart1_2_rx_tx"   "uart"      29, 30
105c115e7f5SFrank Wunderlich          "uart1_2_cts_rts" "uart"      31, 32
10665916a1cSSam Shih          "uart1_1"         "uart"      23, 24, 25, 26
107c115e7f5SFrank Wunderlich          "uart2_0_rx_tx"   "uart"      29, 30
108c115e7f5SFrank Wunderlich          "uart2_0_cts_rts" "uart"      31, 32
10965916a1cSSam Shih          "spi0"            "spi"       33, 34, 35, 36
11065916a1cSSam Shih          "spi0_wp_hold"    "spi"       37, 38
11165916a1cSSam Shih          "uart1_3_rx_tx"   "uart"      35, 36
11265916a1cSSam Shih          "uart1_3_cts_rts" "uart"      37, 38
11365916a1cSSam Shih          "uart2_1"         "uart"      33, 34, 35, 36
11465916a1cSSam Shih          "spi1_3"          "spi"       33, 34, 35, 36
11565916a1cSSam Shih          "uart0"           "uart"      39, 40
11665916a1cSSam Shih          "pcie_pereset"    "pcie"      41
11765916a1cSSam Shih          "uart1"           "uart"      42, 43, 44, 45
11865916a1cSSam Shih          "uart2"           "uart"      46, 47, 48, 49
119c911ad22SArınç ÜNAL          "emmc_51"         "emmc"      50, 51, 52, 53, 54, 55, 56, 57, 58, 59,
120c911ad22SArınç ÜNAL                                        60, 61
121c911ad22SArınç ÜNAL
12265916a1cSSam Shih          "pcm"             "audio"     62, 63, 64, 65
12365916a1cSSam Shih          "i2s"             "audio"     62, 63, 64, 65
12465916a1cSSam Shih          "switch_int"      "eth"       66
12565916a1cSSam Shih          "mdc_mdio"        "eth"       67
12692858eb6SPeter Chiu          "wf_2g"           "wifi"      74, 75, 76, 77, 78, 79, 80, 81, 82, 83
12792858eb6SPeter Chiu          "wf_5g"           "wifi"      91, 92, 93, 94, 95, 96, 97, 98, 99, 100
12892858eb6SPeter Chiu          "wf_dbdc"         "wifi"      74, 75, 76, 77, 78, 79, 80, 81, 82, 83,
12992858eb6SPeter Chiu                                        84, 85
13065916a1cSSam Shih
1316a735ad5SArınç ÜNAL        $ref: /schemas/pinctrl/pinmux-node.yaml
13265916a1cSSam Shih        properties:
13365916a1cSSam Shih          function:
134c911ad22SArınç ÜNAL            description:
13565916a1cSSam Shih              A string containing the name of the function to mux to the group.
13665916a1cSSam Shih              There is no "audio", "pcie" functions on mt7986b, you can only use
13765916a1cSSam Shih              those functions on mt7986a.
13865916a1cSSam Shih            enum: [audio, emmc, eth, i2c, led, flash, pcie, pwm, spi, uart,
13965916a1cSSam Shih                   watchdog, wifi]
14065916a1cSSam Shih          groups:
141c911ad22SArınç ÜNAL            description:
14265916a1cSSam Shih              An array of strings. Each string contains the name of a group.
143c911ad22SArınç ÜNAL              There is no "pcie_pereset", "uart1", "uart2" "emmc_51", "pcm", and
144c911ad22SArınç ÜNAL              "i2s" groups on mt7986b, you can only use those groups on mt7986a.
14565916a1cSSam Shih        required:
14665916a1cSSam Shih          - function
14765916a1cSSam Shih          - groups
14865916a1cSSam Shih
14965916a1cSSam Shih        allOf:
15065916a1cSSam Shih          - if:
15165916a1cSSam Shih              properties:
15265916a1cSSam Shih                function:
15365916a1cSSam Shih                  const: audio
15465916a1cSSam Shih            then:
15565916a1cSSam Shih              properties:
15665916a1cSSam Shih                groups:
15765916a1cSSam Shih                  enum: [pcm, i2s]
15865916a1cSSam Shih          - if:
15965916a1cSSam Shih              properties:
16065916a1cSSam Shih                function:
16165916a1cSSam Shih                  const: emmc
16265916a1cSSam Shih            then:
16365916a1cSSam Shih              properties:
16465916a1cSSam Shih                groups:
165c115e7f5SFrank Wunderlich                  enum: [emmc_45, emmc_51]
16665916a1cSSam Shih          - if:
16765916a1cSSam Shih              properties:
16865916a1cSSam Shih                function:
16965916a1cSSam Shih                  const: eth
17065916a1cSSam Shih            then:
17165916a1cSSam Shih              properties:
17265916a1cSSam Shih                groups:
17365916a1cSSam Shih                  enum: [switch_int, mdc_mdio]
17465916a1cSSam Shih          - if:
17565916a1cSSam Shih              properties:
17665916a1cSSam Shih                function:
17765916a1cSSam Shih                  const: i2c
17865916a1cSSam Shih            then:
17965916a1cSSam Shih              properties:
18065916a1cSSam Shih                groups:
18165916a1cSSam Shih                  enum: [i2c]
18265916a1cSSam Shih          - if:
18365916a1cSSam Shih              properties:
18465916a1cSSam Shih                function:
18565916a1cSSam Shih                  const: led
18665916a1cSSam Shih            then:
18765916a1cSSam Shih              properties:
18865916a1cSSam Shih                groups:
18965916a1cSSam Shih                  enum: [wifi_led]
19065916a1cSSam Shih          - if:
19165916a1cSSam Shih              properties:
19265916a1cSSam Shih                function:
19365916a1cSSam Shih                  const: flash
19465916a1cSSam Shih            then:
19565916a1cSSam Shih              properties:
19665916a1cSSam Shih                groups:
19765916a1cSSam Shih                  enum: [snfi]
19865916a1cSSam Shih          - if:
19965916a1cSSam Shih              properties:
20065916a1cSSam Shih                function:
20165916a1cSSam Shih                  const: pcie
20265916a1cSSam Shih            then:
20365916a1cSSam Shih              properties:
20465916a1cSSam Shih                groups:
205d77a82d6SFrank Wunderlich                  items:
20665916a1cSSam Shih                    enum: [pcie_clk, pcie_wake, pcie_pereset]
207d77a82d6SFrank Wunderlich                  maxItems: 3
20865916a1cSSam Shih          - if:
20965916a1cSSam Shih              properties:
21065916a1cSSam Shih                function:
21165916a1cSSam Shih                  const: pwm
21265916a1cSSam Shih            then:
21365916a1cSSam Shih              properties:
21465916a1cSSam Shih                groups:
215d77a82d6SFrank Wunderlich                  items:
21665916a1cSSam Shih                    enum: [pwm0, pwm1_0, pwm1_1]
217d77a82d6SFrank Wunderlich                  maxItems: 2
21865916a1cSSam Shih          - if:
21965916a1cSSam Shih              properties:
22065916a1cSSam Shih                function:
22165916a1cSSam Shih                  const: spi
22265916a1cSSam Shih            then:
22365916a1cSSam Shih              properties:
22465916a1cSSam Shih                groups:
225d77a82d6SFrank Wunderlich                  items:
22665916a1cSSam Shih                    enum: [spi0, spi0_wp_hold, spi1_0, spi1_1, spi1_2, spi1_3]
227d77a82d6SFrank Wunderlich                  maxItems: 2
22865916a1cSSam Shih          - if:
22965916a1cSSam Shih              properties:
23065916a1cSSam Shih                function:
23165916a1cSSam Shih                  const: uart
23265916a1cSSam Shih            then:
23365916a1cSSam Shih              properties:
23465916a1cSSam Shih                groups:
235c115e7f5SFrank Wunderlich                  items:
236c115e7f5SFrank Wunderlich                    enum: [uart1_0, uart1_rx_tx, uart1_cts_rts, uart1_1,
237c115e7f5SFrank Wunderlich                           uart1_2_rx_tx, uart1_2_cts_rts, uart1_3_rx_tx,
238c115e7f5SFrank Wunderlich                           uart1_3_cts_rts, uart2_0_rx_tx, uart2_0_cts_rts,
239c115e7f5SFrank Wunderlich                           uart2_1, uart0, uart1, uart2]
240c115e7f5SFrank Wunderlich                  maxItems: 2
24165916a1cSSam Shih          - if:
24265916a1cSSam Shih              properties:
24365916a1cSSam Shih                function:
24465916a1cSSam Shih                  const: watchdog
24565916a1cSSam Shih            then:
24665916a1cSSam Shih              properties:
24765916a1cSSam Shih                groups:
24865916a1cSSam Shih                  enum: [watchdog]
24965916a1cSSam Shih          - if:
25065916a1cSSam Shih              properties:
25165916a1cSSam Shih                function:
25265916a1cSSam Shih                  const: wifi
25365916a1cSSam Shih            then:
25465916a1cSSam Shih              properties:
25565916a1cSSam Shih                groups:
25692858eb6SPeter Chiu                  items:
25765916a1cSSam Shih                    enum: [wf_2g, wf_5g, wf_dbdc]
25892858eb6SPeter Chiu                  maxItems: 3
2594b8efbaeSArınç ÜNAL      '^.*conf.*$':
26065916a1cSSam Shih        type: object
26165916a1cSSam Shih        additionalProperties: false
262c911ad22SArınç ÜNAL        description:
26365916a1cSSam Shih          pinconf configuration nodes.
2646a735ad5SArınç ÜNAL        $ref: /schemas/pinctrl/pincfg-node.yaml
26565916a1cSSam Shih
26665916a1cSSam Shih        properties:
26765916a1cSSam Shih          pins:
268c911ad22SArınç ÜNAL            description:
269c911ad22SArınç ÜNAL              An array of strings. Each string contains the name of a pin. There
270c911ad22SArınç ÜNAL              is no PIN 41 to PIN 65 above on mt7686b, you can only use those
271c911ad22SArınç ÜNAL              pins on mt7986a.
27292858eb6SPeter Chiu            items:
27365916a1cSSam Shih              enum: [SYS_WATCHDOG, WF2G_LED, WF5G_LED, I2C_SCL, I2C_SDA, GPIO_0,
27465916a1cSSam Shih                     GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, GPIO_6, GPIO_7,
275c911ad22SArınç ÜNAL                     GPIO_8, GPIO_9, GPIO_10, GPIO_11, GPIO_12, GPIO_13,
276c911ad22SArınç ÜNAL                     GPIO_14, GPIO_15, PWM0, PWM1, SPI0_CLK, SPI0_MOSI,
277c911ad22SArınç ÜNAL                     SPI0_MISO, SPI0_CS, SPI0_HOLD, SPI0_WP, SPI1_CLK,
278c911ad22SArınç ÜNAL                     SPI1_MOSI, SPI1_MISO, SPI1_CS, SPI2_CLK, SPI2_MOSI,
279c911ad22SArınç ÜNAL                     SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP, UART0_RXD,
280c911ad22SArınç ÜNAL                     UART0_TXD, PCIE_PERESET_N, UART1_RXD, UART1_TXD, UART1_CTS,
281c911ad22SArınç ÜNAL                     UART1_RTS, UART2_RXD, UART2_TXD, UART2_CTS, UART2_RTS,
282c911ad22SArınç ÜNAL                     EMMC_DATA_0, EMMC_DATA_1, EMMC_DATA_2, EMMC_DATA_3,
283c911ad22SArınç ÜNAL                     EMMC_DATA_4, EMMC_DATA_5, EMMC_DATA_6, EMMC_DATA_7,
284c911ad22SArınç ÜNAL                     EMMC_CMD, EMMC_CK, EMMC_DSL, EMMC_RSTB, PCM_DTX, PCM_DRX,
285c911ad22SArınç ÜNAL                     PCM_CLK, PCM_FS, MT7531_INT, SMI_MDC, SMI_MDIO,
28665916a1cSSam Shih                     WF0_DIG_RESETB, WF0_CBA_RESETB, WF0_XO_REQ, WF0_TOP_CLK,
28765916a1cSSam Shih                     WF0_TOP_DATA, WF0_HB1, WF0_HB2, WF0_HB3, WF0_HB4, WF0_HB0,
28865916a1cSSam Shih                     WF0_HB0_B, WF0_HB5, WF0_HB6, WF0_HB7, WF0_HB8, WF0_HB9,
28965916a1cSSam Shih                     WF0_HB10, WF1_DIG_RESETB, WF1_CBA_RESETB, WF1_XO_REQ,
29065916a1cSSam Shih                     WF1_TOP_CLK, WF1_TOP_DATA, WF1_HB1, WF1_HB2, WF1_HB3,
29165916a1cSSam Shih                     WF1_HB4, WF1_HB0, WF1_HB0_B, WF1_HB5, WF1_HB6, WF1_HB7,
29265916a1cSSam Shih                     WF1_HB8]
29392858eb6SPeter Chiu            maxItems: 101
29465916a1cSSam Shih
29565916a1cSSam Shih          bias-disable: true
29665916a1cSSam Shih
297e66e66f1SSam Shih          bias-pull-up:
298e66e66f1SSam Shih            oneOf:
299e66e66f1SSam Shih              - type: boolean
300e66e66f1SSam Shih                description: normal pull up.
301e66e66f1SSam Shih              - enum: [100, 101, 102, 103]
302c911ad22SArınç ÜNAL                description:
303e66e66f1SSam Shih                  PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
304e66e66f1SSam Shih                  dt-bindings/pinctrl/mt65xx.h.
30565916a1cSSam Shih
306e66e66f1SSam Shih          bias-pull-down:
307e66e66f1SSam Shih            oneOf:
308e66e66f1SSam Shih              - type: boolean
309e66e66f1SSam Shih                description: normal pull down.
310e66e66f1SSam Shih              - enum: [100, 101, 102, 103]
311c911ad22SArınç ÜNAL                description:
312e66e66f1SSam Shih                  PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
313e66e66f1SSam Shih                  dt-bindings/pinctrl/mt65xx.h.
31465916a1cSSam Shih
31565916a1cSSam Shih          input-enable: true
31665916a1cSSam Shih
31765916a1cSSam Shih          input-disable: true
31865916a1cSSam Shih
31965916a1cSSam Shih          output-enable: true
32065916a1cSSam Shih
32165916a1cSSam Shih          output-low: true
32265916a1cSSam Shih
32365916a1cSSam Shih          output-high: true
32465916a1cSSam Shih
32565916a1cSSam Shih          input-schmitt-enable: true
32665916a1cSSam Shih
32765916a1cSSam Shih          input-schmitt-disable: true
32865916a1cSSam Shih
32965916a1cSSam Shih          drive-strength:
33065916a1cSSam Shih            enum: [2, 4, 6, 8, 10, 12, 14, 16]
33165916a1cSSam Shih
33265916a1cSSam Shih          mediatek,pull-up-adv:
33365916a1cSSam Shih            description: |
33465916a1cSSam Shih              Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
335*47aab533SBjorn Helgaas              Pull up settings for 2 pull resistors, R0 and R1. Valid arguments
33665916a1cSSam Shih              are described as below:
33765916a1cSSam Shih              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
33865916a1cSSam Shih              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
33965916a1cSSam Shih              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
34065916a1cSSam Shih              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
34165916a1cSSam Shih            $ref: /schemas/types.yaml#/definitions/uint32
34265916a1cSSam Shih            enum: [0, 1, 2, 3]
34365916a1cSSam Shih
34465916a1cSSam Shih          mediatek,pull-down-adv:
34565916a1cSSam Shih            description: |
34665916a1cSSam Shih              Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
347*47aab533SBjorn Helgaas              Pull down settings for 2 pull resistors, R0 and R1. Valid arguments
34865916a1cSSam Shih              are described as below:
34965916a1cSSam Shih              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
35065916a1cSSam Shih              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
35165916a1cSSam Shih              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
35265916a1cSSam Shih              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
35365916a1cSSam Shih            $ref: /schemas/types.yaml#/definitions/uint32
35465916a1cSSam Shih            enum: [0, 1, 2, 3]
35565916a1cSSam Shih
35665916a1cSSam Shih        required:
35765916a1cSSam Shih          - pins
35865916a1cSSam Shih
35965916a1cSSam ShihadditionalProperties: false
36065916a1cSSam Shih
36165916a1cSSam Shihexamples:
36265916a1cSSam Shih  - |
36365916a1cSSam Shih    #include <dt-bindings/interrupt-controller/irq.h>
36465916a1cSSam Shih    #include <dt-bindings/interrupt-controller/arm-gic.h>
365e66e66f1SSam Shih    #include <dt-bindings/pinctrl/mt65xx.h>
36665916a1cSSam Shih
36765916a1cSSam Shih    soc {
36865916a1cSSam Shih      #address-cells = <2>;
36965916a1cSSam Shih      #size-cells = <2>;
37065916a1cSSam Shih      pio: pinctrl@1001f000 {
37165916a1cSSam Shih        compatible = "mediatek,mt7986a-pinctrl";
37265916a1cSSam Shih        reg = <0 0x1001f000 0 0x1000>,
37365916a1cSSam Shih              <0 0x11c30000 0 0x1000>,
37465916a1cSSam Shih              <0 0x11c40000 0 0x1000>,
37565916a1cSSam Shih              <0 0x11e20000 0 0x1000>,
37665916a1cSSam Shih              <0 0x11e30000 0 0x1000>,
37765916a1cSSam Shih              <0 0x11f00000 0 0x1000>,
37865916a1cSSam Shih              <0 0x11f10000 0 0x1000>,
37965916a1cSSam Shih              <0 0x1000b000 0 0x1000>;
38065916a1cSSam Shih        reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
38165916a1cSSam Shih                    "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
38265916a1cSSam Shih        gpio-controller;
38365916a1cSSam Shih        #gpio-cells = <2>;
38465916a1cSSam Shih        gpio-ranges = <&pio 0 0 100>;
38565916a1cSSam Shih        interrupt-controller;
38665916a1cSSam Shih        interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
38765916a1cSSam Shih        interrupt-parent = <&gic>;
38865916a1cSSam Shih        #interrupt-cells = <2>;
38965916a1cSSam Shih
390c115e7f5SFrank Wunderlich        pcie_pins: pcie-pins {
391c115e7f5SFrank Wunderlich          mux {
392c115e7f5SFrank Wunderlich            function = "pcie";
393c115e7f5SFrank Wunderlich            groups = "pcie_clk", "pcie_wake", "pcie_pereset";
394c115e7f5SFrank Wunderlich          };
395c115e7f5SFrank Wunderlich        };
396c115e7f5SFrank Wunderlich
397c115e7f5SFrank Wunderlich        pwm_pins: pwm-pins {
398c115e7f5SFrank Wunderlich          mux {
399c115e7f5SFrank Wunderlich            function = "pwm";
400c115e7f5SFrank Wunderlich            groups = "pwm0", "pwm1_0";
401c115e7f5SFrank Wunderlich          };
402c115e7f5SFrank Wunderlich        };
403c115e7f5SFrank Wunderlich
404c115e7f5SFrank Wunderlich        spi0_pins: spi0-pins {
405c115e7f5SFrank Wunderlich          mux {
406c115e7f5SFrank Wunderlich            function = "spi";
407c115e7f5SFrank Wunderlich            groups = "spi0", "spi0_wp_hold";
408c115e7f5SFrank Wunderlich          };
409c115e7f5SFrank Wunderlich        };
410c115e7f5SFrank Wunderlich
41165916a1cSSam Shih        uart1_pins: uart1-pins {
41265916a1cSSam Shih          mux {
41365916a1cSSam Shih            function = "uart";
41465916a1cSSam Shih            groups = "uart1";
41565916a1cSSam Shih          };
41665916a1cSSam Shih        };
41765916a1cSSam Shih
418c115e7f5SFrank Wunderlich        uart1_3_pins: uart1-3-pins {
419c115e7f5SFrank Wunderlich          mux {
420c115e7f5SFrank Wunderlich            function = "uart";
421c115e7f5SFrank Wunderlich            groups = "uart1_3_rx_tx", "uart1_3_cts_rts";
422c115e7f5SFrank Wunderlich          };
423c115e7f5SFrank Wunderlich        };
424c115e7f5SFrank Wunderlich
42565916a1cSSam Shih        uart2_pins: uart2-pins {
42665916a1cSSam Shih          mux {
42765916a1cSSam Shih            function = "uart";
42865916a1cSSam Shih            groups = "uart2";
42965916a1cSSam Shih          };
43065916a1cSSam Shih        };
43165916a1cSSam Shih
432e66e66f1SSam Shih        mmc0_pins_default: mmc0-pins {
433e66e66f1SSam Shih          mux {
434e66e66f1SSam Shih            function = "emmc";
435e66e66f1SSam Shih            groups = "emmc_51";
436e66e66f1SSam Shih          };
437e66e66f1SSam Shih          conf-cmd-dat {
438e66e66f1SSam Shih            pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
439e66e66f1SSam Shih                   "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
440e66e66f1SSam Shih                   "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
441e66e66f1SSam Shih            input-enable;
442e66e66f1SSam Shih            drive-strength = <4>;
443e66e66f1SSam Shih            bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
444e66e66f1SSam Shih          };
445e66e66f1SSam Shih          conf-clk {
446e66e66f1SSam Shih            pins = "EMMC_CK";
447e66e66f1SSam Shih            drive-strength = <6>;
448e66e66f1SSam Shih            bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
449e66e66f1SSam Shih          };
450e66e66f1SSam Shih          conf-ds {
451e66e66f1SSam Shih            pins = "EMMC_DSL";
452e66e66f1SSam Shih            bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
453e66e66f1SSam Shih          };
454e66e66f1SSam Shih          conf-rst {
455e66e66f1SSam Shih            pins = "EMMC_RSTB";
456e66e66f1SSam Shih            drive-strength = <4>;
457e66e66f1SSam Shih            bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
458e66e66f1SSam Shih          };
459e66e66f1SSam Shih        };
460e66e66f1SSam Shih
46165916a1cSSam Shih      };
46265916a1cSSam Shih    };
463