1*a6214218SDong Aisheng* Freescale i.MX7ULP IOMUX Controller 2*a6214218SDong Aisheng 3*a6214218SDong Aishengi.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 4*a6214218SDong Aishengports and IOMUXC DDR for DDR interface. 5*a6214218SDong Aisheng 6*a6214218SDong AishengNote: 7*a6214218SDong AishengThis binding doc is only for the IOMUXC1 support in A7 Domain and it only 8*a6214218SDong Aishengsupports generic pin config. 9*a6214218SDong Aisheng 10*a6214218SDong AishengPlease also refer pinctrl-bindings.txt in this directory for generic pinctrl 11*a6214218SDong Aishengbinding. 12*a6214218SDong Aisheng 13*a6214218SDong Aisheng=== Pin Controller Node === 14*a6214218SDong Aisheng 15*a6214218SDong AishengRequired properties: 16*a6214218SDong Aisheng- compatible: "fsl,imx7ulp-iomuxc1" 17*a6214218SDong Aisheng- reg: Should contain the base physical address and size of the iomuxc 18*a6214218SDong Aisheng registers. 19*a6214218SDong Aisheng 20*a6214218SDong Aisheng=== Pin Configuration Node === 21*a6214218SDong Aisheng- pinmux: One integers array, represents a group of pins mux setting. 22*a6214218SDong Aisheng The format is pinmux = <PIN_FUNC_ID>, PIN_FUNC_ID is a pin working on 23*a6214218SDong Aisheng a specific function. 24*a6214218SDong Aisheng 25*a6214218SDong Aisheng NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux 26*a6214218SDong Aisheng and config register as follows: 27*a6214218SDong Aisheng <mux_conf_reg input_reg mux_mode input_val> 28*a6214218SDong Aisheng 29*a6214218SDong Aisheng Refer to imx7ulp-pinfunc.h in in device tree source folder for all 30*a6214218SDong Aisheng available imx7ulp PIN_FUNC_ID. 31*a6214218SDong Aisheng 32*a6214218SDong AishengOptional Properties: 33*a6214218SDong Aisheng- drive-strength Integer. Controls Drive Strength 34*a6214218SDong Aisheng 0: Standard 35*a6214218SDong Aisheng 1: Hi Driver 36*a6214218SDong Aisheng- drive-push-pull Bool. Enable Pin Push-pull 37*a6214218SDong Aisheng- drive-open-drain Bool. Enable Pin Open-drian 38*a6214218SDong Aisheng- slew-rate: Integer. Controls Slew Rate 39*a6214218SDong Aisheng 0: Standard 40*a6214218SDong Aisheng 1: Slow 41*a6214218SDong Aisheng- bias-disable: Bool. Pull disabled 42*a6214218SDong Aisheng- bias-pull-down: Bool. Pull down on pin 43*a6214218SDong Aisheng- bias-pull-up: Bool. Pull up on pin 44*a6214218SDong Aisheng 45*a6214218SDong AishengExamples: 46*a6214218SDong Aisheng#include "imx7ulp-pinfunc.h" 47*a6214218SDong Aisheng 48*a6214218SDong Aisheng/* Pin Controller Node */ 49*a6214218SDong Aishengiomuxc1: iomuxc@40ac0000 { 50*a6214218SDong Aisheng compatible = "fsl,imx7ulp-iomuxc1"; 51*a6214218SDong Aisheng reg = <0x40ac0000 0x1000>; 52*a6214218SDong Aisheng 53*a6214218SDong Aisheng /* Pin Configuration Node */ 54*a6214218SDong Aisheng pinctrl_lpuart4: lpuart4grp { 55*a6214218SDong Aisheng pinmux = < 56*a6214218SDong Aisheng IMX7ULP_PAD_PTC3__LPUART4_RX 57*a6214218SDong Aisheng IMX7ULP_PAD_PTC2__LPUART4_TX 58*a6214218SDong Aisheng >; 59*a6214218SDong Aisheng bias-pull-up; 60*a6214218SDong Aisheng }; 61*a6214218SDong Aisheng}; 62