xref: /openbmc/linux/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml (revision cea0f76a483d1270ac6f6513964e3e75193dda48)
1*cea0f76aSAnurag Kumar Vulisha# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*cea0f76aSAnurag Kumar Vulisha%YAML 1.2
3*cea0f76aSAnurag Kumar Vulisha---
4*cea0f76aSAnurag Kumar Vulisha$id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml#
5*cea0f76aSAnurag Kumar Vulisha$schema: http://devicetree.org/meta-schemas/core.yaml#
6*cea0f76aSAnurag Kumar Vulisha
7*cea0f76aSAnurag Kumar Vulishatitle: Xilinx ZynqMP Gigabit Transceiver PHY Device Tree Bindings
8*cea0f76aSAnurag Kumar Vulisha
9*cea0f76aSAnurag Kumar Vulishamaintainers:
10*cea0f76aSAnurag Kumar Vulisha  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11*cea0f76aSAnurag Kumar Vulisha
12*cea0f76aSAnurag Kumar Vulishadescription: |
13*cea0f76aSAnurag Kumar Vulisha  This binding describes the Xilinx ZynqMP Gigabit Transceiver (GTR) PHY. The
14*cea0f76aSAnurag Kumar Vulisha  GTR provides four lanes and is used by USB, SATA, PCIE, Display port and
15*cea0f76aSAnurag Kumar Vulisha  Ethernet SGMII controllers.
16*cea0f76aSAnurag Kumar Vulisha
17*cea0f76aSAnurag Kumar Vulishaproperties:
18*cea0f76aSAnurag Kumar Vulisha  "#phy-cells":
19*cea0f76aSAnurag Kumar Vulisha    const: 4
20*cea0f76aSAnurag Kumar Vulisha    description: |
21*cea0f76aSAnurag Kumar Vulisha      The cells contain the following arguments.
22*cea0f76aSAnurag Kumar Vulisha
23*cea0f76aSAnurag Kumar Vulisha      - description: The GTR lane
24*cea0f76aSAnurag Kumar Vulisha        minimum: 0
25*cea0f76aSAnurag Kumar Vulisha        maximum: 3
26*cea0f76aSAnurag Kumar Vulisha      - description: The PHY type
27*cea0f76aSAnurag Kumar Vulisha        enum:
28*cea0f76aSAnurag Kumar Vulisha          - PHY_TYPE_DP
29*cea0f76aSAnurag Kumar Vulisha          - PHY_TYPE_PCIE
30*cea0f76aSAnurag Kumar Vulisha          - PHY_TYPE_SATA
31*cea0f76aSAnurag Kumar Vulisha          - PHY_TYPE_SGMII
32*cea0f76aSAnurag Kumar Vulisha          - PHY_TYPE_USB
33*cea0f76aSAnurag Kumar Vulisha      - description: The PHY instance
34*cea0f76aSAnurag Kumar Vulisha        minimum: 0
35*cea0f76aSAnurag Kumar Vulisha        maximum: 1 # for DP, SATA or USB
36*cea0f76aSAnurag Kumar Vulisha        maximum: 3 # for PCIE or SGMII
37*cea0f76aSAnurag Kumar Vulisha      - description: The reference clock number
38*cea0f76aSAnurag Kumar Vulisha        minimum: 0
39*cea0f76aSAnurag Kumar Vulisha        maximum: 3
40*cea0f76aSAnurag Kumar Vulisha
41*cea0f76aSAnurag Kumar Vulisha  compatible:
42*cea0f76aSAnurag Kumar Vulisha    enum:
43*cea0f76aSAnurag Kumar Vulisha      - xlnx,zynqmp-psgtr-v1.1
44*cea0f76aSAnurag Kumar Vulisha      - xlnx,zynqmp-psgtr
45*cea0f76aSAnurag Kumar Vulisha
46*cea0f76aSAnurag Kumar Vulisha  clocks:
47*cea0f76aSAnurag Kumar Vulisha    minItems: 1
48*cea0f76aSAnurag Kumar Vulisha    maxItems: 4
49*cea0f76aSAnurag Kumar Vulisha    description: |
50*cea0f76aSAnurag Kumar Vulisha      Clock for each PS_MGTREFCLK[0-3] reference clock input. Unconnected
51*cea0f76aSAnurag Kumar Vulisha      inputs shall not have an entry.
52*cea0f76aSAnurag Kumar Vulisha
53*cea0f76aSAnurag Kumar Vulisha  clock-names:
54*cea0f76aSAnurag Kumar Vulisha    minItems: 1
55*cea0f76aSAnurag Kumar Vulisha    maxItems: 4
56*cea0f76aSAnurag Kumar Vulisha    items:
57*cea0f76aSAnurag Kumar Vulisha      pattern: "^ref[0-3]$"
58*cea0f76aSAnurag Kumar Vulisha
59*cea0f76aSAnurag Kumar Vulisha  reg:
60*cea0f76aSAnurag Kumar Vulisha    items:
61*cea0f76aSAnurag Kumar Vulisha      - description: SERDES registers block
62*cea0f76aSAnurag Kumar Vulisha      - description: SIOU registers block
63*cea0f76aSAnurag Kumar Vulisha
64*cea0f76aSAnurag Kumar Vulisha  reg-names:
65*cea0f76aSAnurag Kumar Vulisha    items:
66*cea0f76aSAnurag Kumar Vulisha      - const: serdes
67*cea0f76aSAnurag Kumar Vulisha      - const: siou
68*cea0f76aSAnurag Kumar Vulisha
69*cea0f76aSAnurag Kumar Vulisha  xlnx,tx-termination-fix:
70*cea0f76aSAnurag Kumar Vulisha    description: |
71*cea0f76aSAnurag Kumar Vulisha      Include this for fixing functional issue with the TX termination
72*cea0f76aSAnurag Kumar Vulisha      resistance in GT, which can be out of spec for the XCZU9EG silicon
73*cea0f76aSAnurag Kumar Vulisha      version.
74*cea0f76aSAnurag Kumar Vulisha    type: boolean
75*cea0f76aSAnurag Kumar Vulisha
76*cea0f76aSAnurag Kumar Vulisharequired:
77*cea0f76aSAnurag Kumar Vulisha  - "#phy-cells"
78*cea0f76aSAnurag Kumar Vulisha  - compatible
79*cea0f76aSAnurag Kumar Vulisha  - reg
80*cea0f76aSAnurag Kumar Vulisha  - reg-names
81*cea0f76aSAnurag Kumar Vulisha
82*cea0f76aSAnurag Kumar Vulishaif:
83*cea0f76aSAnurag Kumar Vulisha  properties:
84*cea0f76aSAnurag Kumar Vulisha    compatible:
85*cea0f76aSAnurag Kumar Vulisha      const: xlnx,zynqmp-psgtr-v1.1
86*cea0f76aSAnurag Kumar Vulisha
87*cea0f76aSAnurag Kumar Vulishathen:
88*cea0f76aSAnurag Kumar Vulisha  properties:
89*cea0f76aSAnurag Kumar Vulisha    xlnx,tx-termination-fix: false
90*cea0f76aSAnurag Kumar Vulisha
91*cea0f76aSAnurag Kumar VulishaadditionalProperties: false
92*cea0f76aSAnurag Kumar Vulisha
93*cea0f76aSAnurag Kumar Vulishaexamples:
94*cea0f76aSAnurag Kumar Vulisha  - |
95*cea0f76aSAnurag Kumar Vulisha    phy: phy@fd400000 {
96*cea0f76aSAnurag Kumar Vulisha        compatible = "xlnx,zynqmp-psgtr-v1.1";
97*cea0f76aSAnurag Kumar Vulisha        reg = <0x0 0xfd400000 0x0 0x40000>,
98*cea0f76aSAnurag Kumar Vulisha              <0x0 0xfd3d0000 0x0 0x1000>;
99*cea0f76aSAnurag Kumar Vulisha        reg-names = "serdes", "siou";
100*cea0f76aSAnurag Kumar Vulisha        clocks = <&refclks 3>, <&refclks 2>, <&refclks 0>;
101*cea0f76aSAnurag Kumar Vulisha        clock-names = "ref1", "ref2", "ref3";
102*cea0f76aSAnurag Kumar Vulisha        #phy-cells = <4>;
103*cea0f76aSAnurag Kumar Vulisha    };
104*cea0f76aSAnurag Kumar Vulisha
105*cea0f76aSAnurag Kumar Vulisha...
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