1*dea54fbaSHauke MehrtensLantiq XWAY SoC RCU USB 1.1/2.0 PHY binding 2*dea54fbaSHauke Mehrtens=========================================== 3*dea54fbaSHauke Mehrtens 4*dea54fbaSHauke MehrtensThis binding describes the USB PHY hardware provided by the RCU module on the 5*dea54fbaSHauke MehrtensLantiq XWAY SoCs. 6*dea54fbaSHauke Mehrtens 7*dea54fbaSHauke MehrtensThis node has to be a sub node of the Lantiq RCU block. 8*dea54fbaSHauke Mehrtens 9*dea54fbaSHauke Mehrtens------------------------------------------------------------------------------- 10*dea54fbaSHauke MehrtensRequired properties (controller (parent) node): 11*dea54fbaSHauke Mehrtens- compatible : Should be one of 12*dea54fbaSHauke Mehrtens "lantiq,ase-usb2-phy" 13*dea54fbaSHauke Mehrtens "lantiq,danube-usb2-phy" 14*dea54fbaSHauke Mehrtens "lantiq,xrx100-usb2-phy" 15*dea54fbaSHauke Mehrtens "lantiq,xrx200-usb2-phy" 16*dea54fbaSHauke Mehrtens "lantiq,xrx300-usb2-phy" 17*dea54fbaSHauke Mehrtens- reg : Defines the following sets of registers in the parent 18*dea54fbaSHauke Mehrtens syscon device 19*dea54fbaSHauke Mehrtens - Offset of the USB PHY configuration register 20*dea54fbaSHauke Mehrtens - Offset of the USB Analog configuration 21*dea54fbaSHauke Mehrtens register (only for xrx200 and xrx200) 22*dea54fbaSHauke Mehrtens- clocks : References to the (PMU) "phy" clk gate. 23*dea54fbaSHauke Mehrtens- clock-names : Must be "phy" 24*dea54fbaSHauke Mehrtens- resets : References to the RCU USB configuration reset bits. 25*dea54fbaSHauke Mehrtens- reset-names : Must be one of the following: 26*dea54fbaSHauke Mehrtens "phy" (optional) 27*dea54fbaSHauke Mehrtens "ctrl" (shared) 28*dea54fbaSHauke Mehrtens 29*dea54fbaSHauke Mehrtens------------------------------------------------------------------------------- 30*dea54fbaSHauke MehrtensExample for the USB PHYs on an xRX200 SoC: 31*dea54fbaSHauke Mehrtens usb_phy0: usb2-phy@18 { 32*dea54fbaSHauke Mehrtens compatible = "lantiq,xrx200-usb2-phy"; 33*dea54fbaSHauke Mehrtens reg = <0x18 4>, <0x38 4>; 34*dea54fbaSHauke Mehrtens 35*dea54fbaSHauke Mehrtens clocks = <&pmu PMU_GATE_USB0_PHY>; 36*dea54fbaSHauke Mehrtens clock-names = "phy"; 37*dea54fbaSHauke Mehrtens resets = <&reset1 4 4>, <&reset0 4 4>; 38*dea54fbaSHauke Mehrtens reset-names = "phy", "ctrl"; 39*dea54fbaSHauke Mehrtens #phy-cells = <0>; 40*dea54fbaSHauke Mehrtens }; 41