1*d0aa1608SIcenowy Zheng# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*d0aa1608SIcenowy Zheng%YAML 1.2 3*d0aa1608SIcenowy Zheng--- 4*d0aa1608SIcenowy Zheng$id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml# 5*d0aa1608SIcenowy Zheng$schema: http://devicetree.org/meta-schemas/core.yaml# 6*d0aa1608SIcenowy Zheng 7*d0aa1608SIcenowy Zhengtitle: Allwinner F1C100s USB PHY 8*d0aa1608SIcenowy Zheng 9*d0aa1608SIcenowy Zhengmaintainers: 10*d0aa1608SIcenowy Zheng - Chen-Yu Tsai <wens@csie.org> 11*d0aa1608SIcenowy Zheng - Maxime Ripard <mripard@kernel.org> 12*d0aa1608SIcenowy Zheng 13*d0aa1608SIcenowy Zhengproperties: 14*d0aa1608SIcenowy Zheng "#phy-cells": 15*d0aa1608SIcenowy Zheng const: 1 16*d0aa1608SIcenowy Zheng 17*d0aa1608SIcenowy Zheng compatible: 18*d0aa1608SIcenowy Zheng const: allwinner,suniv-f1c100s-usb-phy 19*d0aa1608SIcenowy Zheng 20*d0aa1608SIcenowy Zheng reg: 21*d0aa1608SIcenowy Zheng maxItems: 1 22*d0aa1608SIcenowy Zheng description: PHY Control registers 23*d0aa1608SIcenowy Zheng 24*d0aa1608SIcenowy Zheng reg-names: 25*d0aa1608SIcenowy Zheng const: phy_ctrl 26*d0aa1608SIcenowy Zheng 27*d0aa1608SIcenowy Zheng clocks: 28*d0aa1608SIcenowy Zheng maxItems: 1 29*d0aa1608SIcenowy Zheng description: USB OTG PHY bus clock 30*d0aa1608SIcenowy Zheng 31*d0aa1608SIcenowy Zheng clock-names: 32*d0aa1608SIcenowy Zheng const: usb0_phy 33*d0aa1608SIcenowy Zheng 34*d0aa1608SIcenowy Zheng resets: 35*d0aa1608SIcenowy Zheng maxItems: 1 36*d0aa1608SIcenowy Zheng description: USB OTG reset 37*d0aa1608SIcenowy Zheng 38*d0aa1608SIcenowy Zheng reset-names: 39*d0aa1608SIcenowy Zheng const: usb0_reset 40*d0aa1608SIcenowy Zheng 41*d0aa1608SIcenowy Zheng usb0_id_det-gpios: 42*d0aa1608SIcenowy Zheng maxItems: 1 43*d0aa1608SIcenowy Zheng description: GPIO to the USB OTG ID pin 44*d0aa1608SIcenowy Zheng 45*d0aa1608SIcenowy Zheng usb0_vbus_det-gpios: 46*d0aa1608SIcenowy Zheng maxItems: 1 47*d0aa1608SIcenowy Zheng description: GPIO to the USB OTG VBUS detect pin 48*d0aa1608SIcenowy Zheng 49*d0aa1608SIcenowy Zheng usb0_vbus_power-supply: 50*d0aa1608SIcenowy Zheng description: Power supply to detect the USB OTG VBUS 51*d0aa1608SIcenowy Zheng 52*d0aa1608SIcenowy Zheng usb0_vbus-supply: 53*d0aa1608SIcenowy Zheng description: Regulator controlling USB OTG VBUS 54*d0aa1608SIcenowy Zheng 55*d0aa1608SIcenowy Zhengrequired: 56*d0aa1608SIcenowy Zheng - "#phy-cells" 57*d0aa1608SIcenowy Zheng - compatible 58*d0aa1608SIcenowy Zheng - clocks 59*d0aa1608SIcenowy Zheng - clock-names 60*d0aa1608SIcenowy Zheng - reg 61*d0aa1608SIcenowy Zheng - reg-names 62*d0aa1608SIcenowy Zheng - resets 63*d0aa1608SIcenowy Zheng - reset-names 64*d0aa1608SIcenowy Zheng 65*d0aa1608SIcenowy ZhengadditionalProperties: false 66*d0aa1608SIcenowy Zheng 67*d0aa1608SIcenowy Zhengexamples: 68*d0aa1608SIcenowy Zheng - | 69*d0aa1608SIcenowy Zheng #include <dt-bindings/gpio/gpio.h> 70*d0aa1608SIcenowy Zheng #include <dt-bindings/clock/suniv-ccu-f1c100s.h> 71*d0aa1608SIcenowy Zheng #include <dt-bindings/reset/suniv-ccu-f1c100s.h> 72*d0aa1608SIcenowy Zheng 73*d0aa1608SIcenowy Zheng phy@1c13400 { 74*d0aa1608SIcenowy Zheng compatible = "allwinner,suniv-f1c100s-usb-phy"; 75*d0aa1608SIcenowy Zheng reg = <0x01c13400 0x10>; 76*d0aa1608SIcenowy Zheng reg-names = "phy_ctrl"; 77*d0aa1608SIcenowy Zheng clocks = <&ccu CLK_USB_PHY0>; 78*d0aa1608SIcenowy Zheng clock-names = "usb0_phy"; 79*d0aa1608SIcenowy Zheng resets = <&ccu RST_USB_PHY0>; 80*d0aa1608SIcenowy Zheng reset-names = "usb0_reset"; 81*d0aa1608SIcenowy Zheng #phy-cells = <1>; 82*d0aa1608SIcenowy Zheng usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>; 83*d0aa1608SIcenowy Zheng }; 84