1*3edeb495SHou ZhiqiangNXP Layerscape PCIe Gen4 controller 2*3edeb495SHou Zhiqiang 3*3edeb495SHou ZhiqiangThis PCIe controller is based on the Mobiveil PCIe IP and thus inherits all 4*3edeb495SHou Zhiqiangthe common properties defined in mobiveil-pcie.txt. 5*3edeb495SHou Zhiqiang 6*3edeb495SHou ZhiqiangRequired properties: 7*3edeb495SHou Zhiqiang- compatible: should contain the platform identifier such as: 8*3edeb495SHou Zhiqiang "fsl,lx2160a-pcie" 9*3edeb495SHou Zhiqiang- reg: base addresses and lengths of the PCIe controller register blocks. 10*3edeb495SHou Zhiqiang "csr_axi_slave": Bridge config registers 11*3edeb495SHou Zhiqiang "config_axi_slave": PCIe controller registers 12*3edeb495SHou Zhiqiang- interrupts: A list of interrupt outputs of the controller. Must contain an 13*3edeb495SHou Zhiqiang entry for each entry in the interrupt-names property. 14*3edeb495SHou Zhiqiang- interrupt-names: It could include the following entries: 15*3edeb495SHou Zhiqiang "intr": The interrupt that is asserted for controller interrupts 16*3edeb495SHou Zhiqiang "aer": Asserted for aer interrupt when chip support the aer interrupt with 17*3edeb495SHou Zhiqiang none MSI/MSI-X/INTx mode,but there is interrupt line for aer. 18*3edeb495SHou Zhiqiang "pme": Asserted for pme interrupt when chip support the pme interrupt with 19*3edeb495SHou Zhiqiang none MSI/MSI-X/INTx mode,but there is interrupt line for pme. 20*3edeb495SHou Zhiqiang- dma-coherent: Indicates that the hardware IP block can ensure the coherency 21*3edeb495SHou Zhiqiang of the data transferred from/to the IP block. This can avoid the software 22*3edeb495SHou Zhiqiang cache flush/invalid actions, and improve the performance significantly. 23*3edeb495SHou Zhiqiang- msi-parent : See the generic MSI binding described in 24*3edeb495SHou Zhiqiang Documentation/devicetree/bindings/interrupt-controller/msi.txt. 25*3edeb495SHou Zhiqiang 26*3edeb495SHou ZhiqiangExample: 27*3edeb495SHou Zhiqiang 28*3edeb495SHou Zhiqiang pcie@3400000 { 29*3edeb495SHou Zhiqiang compatible = "fsl,lx2160a-pcie"; 30*3edeb495SHou Zhiqiang reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 31*3edeb495SHou Zhiqiang 0x80 0x00000000 0x0 0x00001000>; /* configuration space */ 32*3edeb495SHou Zhiqiang reg-names = "csr_axi_slave", "config_axi_slave"; 33*3edeb495SHou Zhiqiang interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 34*3edeb495SHou Zhiqiang <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 35*3edeb495SHou Zhiqiang <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 36*3edeb495SHou Zhiqiang interrupt-names = "aer", "pme", "intr"; 37*3edeb495SHou Zhiqiang #address-cells = <3>; 38*3edeb495SHou Zhiqiang #size-cells = <2>; 39*3edeb495SHou Zhiqiang device_type = "pci"; 40*3edeb495SHou Zhiqiang apio-wins = <8>; 41*3edeb495SHou Zhiqiang ppio-wins = <8>; 42*3edeb495SHou Zhiqiang dma-coherent; 43*3edeb495SHou Zhiqiang bus-range = <0x0 0xff>; 44*3edeb495SHou Zhiqiang msi-parent = <&its>; 45*3edeb495SHou Zhiqiang ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; 46*3edeb495SHou Zhiqiang #interrupt-cells = <1>; 47*3edeb495SHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 48*3edeb495SHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 49*3edeb495SHou Zhiqiang <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 50*3edeb495SHou Zhiqiang <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 51*3edeb495SHou Zhiqiang <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 52*3edeb495SHou Zhiqiang }; 53