1*4020d07eSAriel D'Alessandro* NXP LPC18xx EEPROM memory NVMEM driver 2*4020d07eSAriel D'Alessandro 3*4020d07eSAriel D'AlessandroRequired properties: 4*4020d07eSAriel D'Alessandro - compatible: Should be "nxp,lpc1857-eeprom" 5*4020d07eSAriel D'Alessandro - reg: Must contain an entry with the physical base address and length 6*4020d07eSAriel D'Alessandro for each entry in reg-names. 7*4020d07eSAriel D'Alessandro - reg-names: Must include the following entries. 8*4020d07eSAriel D'Alessandro - reg: EEPROM registers. 9*4020d07eSAriel D'Alessandro - mem: EEPROM address space. 10*4020d07eSAriel D'Alessandro - clocks: Must contain an entry for each entry in clock-names. 11*4020d07eSAriel D'Alessandro - clock-names: Must include the following entries. 12*4020d07eSAriel D'Alessandro - eeprom: EEPROM operating clock. 13*4020d07eSAriel D'Alessandro - resets: Should contain a reference to the reset controller asserting 14*4020d07eSAriel D'Alessandro the EEPROM in reset. 15*4020d07eSAriel D'Alessandro - interrupts: Should contain EEPROM interrupt. 16*4020d07eSAriel D'Alessandro 17*4020d07eSAriel D'AlessandroExample: 18*4020d07eSAriel D'Alessandro 19*4020d07eSAriel D'Alessandro eeprom: eeprom@4000e000 { 20*4020d07eSAriel D'Alessandro compatible = "nxp,lpc1857-eeprom"; 21*4020d07eSAriel D'Alessandro reg = <0x4000e000 0x1000>, 22*4020d07eSAriel D'Alessandro <0x20040000 0x4000>; 23*4020d07eSAriel D'Alessandro reg-names = "reg", "mem"; 24*4020d07eSAriel D'Alessandro clocks = <&ccu1 CLK_CPU_EEPROM>; 25*4020d07eSAriel D'Alessandro clock-names = "eeprom"; 26*4020d07eSAriel D'Alessandro resets = <&rgu 27>; 27*4020d07eSAriel D'Alessandro interrupts = <4>; 28*4020d07eSAriel D'Alessandro }; 29