xref: /openbmc/linux/Documentation/devicetree/bindings/net/toshiba,visconti-dwmac.yaml (revision 1ac731c529cd4d6adbce134754b51ff7d822b145)

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/toshiba,visconti-dwmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Toshiba Visconti DWMAC Ethernet controller

maintainers:
  - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>

select:
  properties:
    compatible:
      contains:
        enum:
          - toshiba,visconti-dwmac
  required:
    - compatible

allOf:
  - $ref: snps,dwmac.yaml#

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - toshiba,visconti-dwmac
          - const: snps,dwmac-4.20a

  reg:
    maxItems: 1

  clocks:
    items:
      - description: main clock
      - description: PHY reference clock

  clock-names:
    items:
      - const: stmmaceth
      - const: phy_ref_clk

required:
  - compatible
  - reg
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/toshiba,tmpv770x.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        piether: ethernet@28000000 {
            compatible = "toshiba,visconti-dwmac", "snps,dwmac-4.20a";
            reg = <0 0x28000000 0 0x10000>;
            interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "macirq";
            clocks = <&pismu TMPV770X_CLK_PIETHER_BUS>, <&pismu TMPV770X_CLK_PIETHER_125M>;
            clock-names = "stmmaceth", "phy_ref_clk";
            snps,txpbl = <4>;
            snps,rxpbl = <4>;
            snps,tso;
            phy-mode = "rgmii-id";
            phy-handle = <&phy0>;

            mdio {
                #address-cells = <0x1>;
                #size-cells = <0x0>;
                compatible = "snps,dwmac-mdio";

                phy0: ethernet-phy@1 {
                    device_type = "ethernet-phy";
                    reg = <0x1>;
                };
            };
        };
    };