xref: /openbmc/linux/Documentation/devicetree/bindings/net/sti-dwmac.txt (revision d15891ca1fdd7f1f46cede1dc15bcfbf0445a658)
1*d15891caSSrinivas KandagatlaSTMicroelectronics SoC DWMAC glue layer controller
2*d15891caSSrinivas Kandagatla
3*d15891caSSrinivas KandagatlaThe device node has following properties.
4*d15891caSSrinivas Kandagatla
5*d15891caSSrinivas KandagatlaRequired properties:
6*d15891caSSrinivas Kandagatla - compatible	: Can be "st,stih415-dwmac", "st,stih416-dwmac" or
7*d15891caSSrinivas Kandagatla   "st,stid127-dwmac".
8*d15891caSSrinivas Kandagatla - reg		: Offset of the glue configuration register map in system
9*d15891caSSrinivas Kandagatla   configuration regmap pointed by st,syscon property and size.
10*d15891caSSrinivas Kandagatla
11*d15891caSSrinivas Kandagatla - reg-names	: Should be "sti-ethconf".
12*d15891caSSrinivas Kandagatla
13*d15891caSSrinivas Kandagatla - st,syscon	: Should be phandle to system configuration node which
14*d15891caSSrinivas Kandagatla   encompases this glue registers.
15*d15891caSSrinivas Kandagatla
16*d15891caSSrinivas Kandagatla - st,tx-retime-src: On STi Parts for Giga bit speeds, 125Mhz clocks can be
17*d15891caSSrinivas Kandagatla   wired up in from different sources. One via TXCLK pin and other via CLK_125
18*d15891caSSrinivas Kandagatla   pin. This wiring is totally board dependent. However the retiming glue
19*d15891caSSrinivas Kandagatla   logic should be configured accordingly. Possible values for this property
20*d15891caSSrinivas Kandagatla
21*d15891caSSrinivas Kandagatla	   "txclk" - if 125Mhz clock is wired up via txclk line.
22*d15891caSSrinivas Kandagatla	   "clk_125" - if 125Mhz clock is wired up via clk_125 line.
23*d15891caSSrinivas Kandagatla
24*d15891caSSrinivas Kandagatla   This property is only valid for Giga bit setup( GMII, RGMII), and it is
25*d15891caSSrinivas Kandagatla   un-used for non-giga bit (MII and RMII) setups. Also note that internal
26*d15891caSSrinivas Kandagatla   clockgen can not generate stable 125Mhz clock.
27*d15891caSSrinivas Kandagatla
28*d15891caSSrinivas Kandagatla - st,ext-phyclk: This boolean property indicates who is generating the clock
29*d15891caSSrinivas Kandagatla  for tx and rx. This property is only valid for RMII case where the clock can
30*d15891caSSrinivas Kandagatla  be generated from the MAC or PHY.
31*d15891caSSrinivas Kandagatla
32*d15891caSSrinivas Kandagatla - clock-names: should be "sti-ethclk".
33*d15891caSSrinivas Kandagatla - clocks: Should point to ethernet clockgen which can generate phyclk.
34*d15891caSSrinivas Kandagatla
35*d15891caSSrinivas Kandagatla
36*d15891caSSrinivas KandagatlaExample:
37*d15891caSSrinivas Kandagatla
38*d15891caSSrinivas Kandagatlaethernet0: dwmac@fe810000 {
39*d15891caSSrinivas Kandagatla	device_type 	= "network";
40*d15891caSSrinivas Kandagatla	compatible	= "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
41*d15891caSSrinivas Kandagatla	reg 		= <0xfe810000 0x8000>, <0x8bc 0x4>;
42*d15891caSSrinivas Kandagatla	reg-names	= "stmmaceth", "sti-ethconf";
43*d15891caSSrinivas Kandagatla	interrupts	= <0 133 0>, <0 134 0>, <0 135 0>;
44*d15891caSSrinivas Kandagatla	interrupt-names	= "macirq", "eth_wake_irq", "eth_lpi";
45*d15891caSSrinivas Kandagatla	phy-mode	= "mii";
46*d15891caSSrinivas Kandagatla
47*d15891caSSrinivas Kandagatla	st,syscon	= <&syscfg_rear>;
48*d15891caSSrinivas Kandagatla
49*d15891caSSrinivas Kandagatla	snps,pbl 	= <32>;
50*d15891caSSrinivas Kandagatla	snps,mixed-burst;
51*d15891caSSrinivas Kandagatla
52*d15891caSSrinivas Kandagatla	resets		= <&softreset STIH416_ETH0_SOFTRESET>;
53*d15891caSSrinivas Kandagatla	reset-names	= "stmmaceth";
54*d15891caSSrinivas Kandagatla	pinctrl-0	= <&pinctrl_mii0>;
55*d15891caSSrinivas Kandagatla	pinctrl-names 	= "default";
56*d15891caSSrinivas Kandagatla	clocks		= <&CLK_S_GMAC0_PHY>;
57*d15891caSSrinivas Kandagatla	clock-names	= "stmmaceth";
58*d15891caSSrinivas Kandagatla};
59