1d15891caSSrinivas KandagatlaSTMicroelectronics SoC DWMAC glue layer controller 2d15891caSSrinivas Kandagatla 353b26b9bSGiuseppe CAVALLAROThis file documents differences between the core properties in 453b26b9bSGiuseppe CAVALLARODocumentation/devicetree/bindings/net/stmmac.txt 553b26b9bSGiuseppe CAVALLAROand what is needed on STi platforms to program the stmmac glue logic. 653b26b9bSGiuseppe CAVALLARO 7d15891caSSrinivas KandagatlaThe device node has following properties. 8d15891caSSrinivas Kandagatla 9d15891caSSrinivas KandagatlaRequired properties: 103f90faa3SAlain Volmat - compatible : "st,stih407-dwmac" 119b1a6d36SPeter Griffin - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which 129b1a6d36SPeter Griffin encompases the glue register, and the offset of the control register. 1353b26b9bSGiuseppe CAVALLARO - st,gmac_en: this is to enable the gmac into a dedicated sysctl control 1453b26b9bSGiuseppe CAVALLARO register available on STiH407 SoC. 1553b26b9bSGiuseppe CAVALLARO - pinctrl-0: pin-control for all the MII mode supported. 16d15891caSSrinivas Kandagatla 1753b26b9bSGiuseppe CAVALLAROOptional properties: 1853b26b9bSGiuseppe CAVALLARO - resets : phandle pointing to the system reset controller with correct 1953b26b9bSGiuseppe CAVALLARO reset line index for ethernet reset. 2053b26b9bSGiuseppe CAVALLARO - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or 2153b26b9bSGiuseppe CAVALLARO MAC can generate it. 2253b26b9bSGiuseppe CAVALLARO - st,tx-retime-src: This specifies which clk is wired up to the mac for 2353b26b9bSGiuseppe CAVALLARO retimeing tx lines. This is totally board dependent and can take one of the 24*47aab533SBjorn Helgaas possible values from "txclk", "clk_125" or "clkgen". 2553b26b9bSGiuseppe CAVALLARO If not passed, the internal clock will be used by default. 2653b26b9bSGiuseppe CAVALLARO - sti-ethclk: this is the phy clock. 2753b26b9bSGiuseppe CAVALLARO - sti-clkconf: this is an extra sysconfig register, available in new SoCs, 2853b26b9bSGiuseppe CAVALLARO to program the clk retiming. 2953b26b9bSGiuseppe CAVALLARO - st,gmac_en: to enable the GMAC, this only is present in some SoCs; e.g. 3053b26b9bSGiuseppe CAVALLARO STiH407. 31d15891caSSrinivas Kandagatla 32d15891caSSrinivas KandagatlaExample: 33d15891caSSrinivas Kandagatla 3453b26b9bSGiuseppe CAVALLAROethernet0: dwmac@9630000 { 35d15891caSSrinivas Kandagatla device_type = "network"; 3653b26b9bSGiuseppe CAVALLARO compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710"; 379b1a6d36SPeter Griffin reg = <0x9630000 0x8000>; 389b1a6d36SPeter Griffin reg-names = "stmmaceth"; 39d15891caSSrinivas Kandagatla 409b1a6d36SPeter Griffin st,syscon = <&syscfg_sbc_reg 0x80>; 4153b26b9bSGiuseppe CAVALLARO st,gmac_en; 4253b26b9bSGiuseppe CAVALLARO resets = <&softreset STIH407_ETH1_SOFTRESET>; 4353b26b9bSGiuseppe CAVALLARO reset-names = "stmmaceth"; 4453b26b9bSGiuseppe CAVALLARO 4553b26b9bSGiuseppe CAVALLARO interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>, 4653b26b9bSGiuseppe CAVALLARO <GIC_SPI 99 IRQ_TYPE_NONE>, 4753b26b9bSGiuseppe CAVALLARO <GIC_SPI 100 IRQ_TYPE_NONE>; 4853b26b9bSGiuseppe CAVALLARO interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; 49d15891caSSrinivas Kandagatla 50d15891caSSrinivas Kandagatla snps,pbl = <32>; 51d15891caSSrinivas Kandagatla snps,mixed-burst; 52d15891caSSrinivas Kandagatla 53d15891caSSrinivas Kandagatla pinctrl-names = "default"; 5453b26b9bSGiuseppe CAVALLARO pinctrl-0 = <&pinctrl_rgmii1>; 5553b26b9bSGiuseppe CAVALLARO 5653b26b9bSGiuseppe CAVALLARO clock-names = "stmmaceth", "sti-ethclk"; 5753b26b9bSGiuseppe CAVALLARO clocks = <&CLK_S_C0_FLEXGEN CLK_EXT2F_A9>, 5853b26b9bSGiuseppe CAVALLARO <&CLK_S_C0_FLEXGEN CLK_ETH_PHY>; 59d15891caSSrinivas Kandagatla}; 60