12755e187SDinh NguyenAltera SOCFPGA SoC DWMAC controller 22755e187SDinh Nguyen 32755e187SDinh NguyenThis is a variant of the dwmac/stmmac driver an inherits all descriptions 42755e187SDinh Nguyenpresent in Documentation/devicetree/bindings/net/stmmac.txt. 52755e187SDinh Nguyen 62755e187SDinh NguyenThe device node has additional properties: 72755e187SDinh Nguyen 82755e187SDinh NguyenRequired properties: 92755e187SDinh Nguyen - compatible : Should contain "altr,socfpga-stmmac" along with 102755e187SDinh Nguyen "snps,dwmac" and any applicable more detailed 112755e187SDinh Nguyen designware version numbers documented in stmmac.txt 122755e187SDinh Nguyen - altr,sysmgr-syscon : Should be the phandle to the system manager node that 132755e187SDinh Nguyen encompasses the glue register, the register offset, and the register shift. 1443569814SPhil Reid - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock 1543569814SPhil Reid for ptp ref clk. This affects all emacs as the clock is common. 162755e187SDinh Nguyen 17b4834c86SLey Foon TanOptional properties: 18b4834c86SLey Foon Tanaltr,emac-splitter: Should be the phandle to the emac splitter soft IP node if 19b4834c86SLey Foon Tan DWMAC controller is connected emac splitter. 20*fb3bbdb8STien Hock Lohphy-mode: The phy mode the ethernet operates in 21*fb3bbdb8STien Hock Lohaltr,sgmii-to-sgmii-converter: phandle to the TSE SGMII converter 22*fb3bbdb8STien Hock Loh 23*fb3bbdb8STien Hock LohThis device node has additional phandle dependency, the sgmii converter: 24*fb3bbdb8STien Hock Loh 25*fb3bbdb8STien Hock LohRequired properties: 26*fb3bbdb8STien Hock Loh - compatible : Should be altr,gmii-to-sgmii-2.0 27*fb3bbdb8STien Hock Loh - reg-names : Should be "eth_tse_control_port" 28b4834c86SLey Foon Tan 292755e187SDinh NguyenExample: 302755e187SDinh Nguyen 31*fb3bbdb8STien Hock Lohgmii_to_sgmii_converter: phy@0x100000240 { 32*fb3bbdb8STien Hock Loh compatible = "altr,gmii-to-sgmii-2.0"; 33*fb3bbdb8STien Hock Loh reg = <0x00000001 0x00000240 0x00000008>, 34*fb3bbdb8STien Hock Loh <0x00000001 0x00000200 0x00000040>; 35*fb3bbdb8STien Hock Loh reg-names = "eth_tse_control_port"; 36*fb3bbdb8STien Hock Loh clocks = <&sgmii_1_clk_0 &emac1 1 &sgmii_clk_125 &sgmii_clk_125>; 37*fb3bbdb8STien Hock Loh clock-names = "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk"; 38*fb3bbdb8STien Hock Loh}; 39*fb3bbdb8STien Hock Loh 402755e187SDinh Nguyengmac0: ethernet@ff700000 { 412755e187SDinh Nguyen compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; 422755e187SDinh Nguyen altr,sysmgr-syscon = <&sysmgr 0x60 0>; 432755e187SDinh Nguyen status = "disabled"; 442755e187SDinh Nguyen reg = <0xff700000 0x2000>; 452755e187SDinh Nguyen interrupts = <0 115 4>; 462755e187SDinh Nguyen interrupt-names = "macirq"; 472755e187SDinh Nguyen mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ 482755e187SDinh Nguyen clocks = <&emac_0_clk>; 49ae107d06SGeert Uytterhoeven clock-names = "stmmaceth"; 50*fb3bbdb8STien Hock Loh phy-mode = "sgmii"; 51*fb3bbdb8STien Hock Loh altr,gmii-to-sgmii-converter = <&gmii_to_sgmii_converter>; 522755e187SDinh Nguyen}; 53