12755e187SDinh NguyenAltera SOCFPGA SoC DWMAC controller 22755e187SDinh Nguyen 32755e187SDinh NguyenThis is a variant of the dwmac/stmmac driver an inherits all descriptions 42755e187SDinh Nguyenpresent in Documentation/devicetree/bindings/net/stmmac.txt. 52755e187SDinh Nguyen 62755e187SDinh NguyenThe device node has additional properties: 72755e187SDinh Nguyen 82755e187SDinh NguyenRequired properties: 9*b637e085SDinh Nguyen - compatible : For Cyclone5/Arria5 SoCs it should contain 10*b637e085SDinh Nguyen "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs 11*b637e085SDinh Nguyen "altr,socfpga-stmmac-a10-s10". 12*b637e085SDinh Nguyen Along with "snps,dwmac" and any applicable more detailed 132755e187SDinh Nguyen designware version numbers documented in stmmac.txt 142755e187SDinh Nguyen - altr,sysmgr-syscon : Should be the phandle to the system manager node that 152755e187SDinh Nguyen encompasses the glue register, the register offset, and the register shift. 16*b637e085SDinh Nguyen On Cyclone5/Arria5, the register shift represents the PHY mode bits, while 17*b637e085SDinh Nguyen on the Arria10/Stratix10/Agilex platforms, the register shift represents 18*b637e085SDinh Nguyen bit for each emac to enable/disable signals from the FPGA fabric to the 19*b637e085SDinh Nguyen EMAC modules. 2043569814SPhil Reid - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock 2143569814SPhil Reid for ptp ref clk. This affects all emacs as the clock is common. 222755e187SDinh Nguyen 23b4834c86SLey Foon TanOptional properties: 24b4834c86SLey Foon Tanaltr,emac-splitter: Should be the phandle to the emac splitter soft IP node if 25b4834c86SLey Foon Tan DWMAC controller is connected emac splitter. 26fb3bbdb8STien Hock Lohphy-mode: The phy mode the ethernet operates in 27fb3bbdb8STien Hock Lohaltr,sgmii-to-sgmii-converter: phandle to the TSE SGMII converter 28fb3bbdb8STien Hock Loh 29fb3bbdb8STien Hock LohThis device node has additional phandle dependency, the sgmii converter: 30fb3bbdb8STien Hock Loh 31fb3bbdb8STien Hock LohRequired properties: 32fb3bbdb8STien Hock Loh - compatible : Should be altr,gmii-to-sgmii-2.0 33fb3bbdb8STien Hock Loh - reg-names : Should be "eth_tse_control_port" 34b4834c86SLey Foon Tan 352755e187SDinh NguyenExample: 362755e187SDinh Nguyen 374c9847b7SMathieu Malaterregmii_to_sgmii_converter: phy@100000240 { 38fb3bbdb8STien Hock Loh compatible = "altr,gmii-to-sgmii-2.0"; 39fb3bbdb8STien Hock Loh reg = <0x00000001 0x00000240 0x00000008>, 40fb3bbdb8STien Hock Loh <0x00000001 0x00000200 0x00000040>; 41fb3bbdb8STien Hock Loh reg-names = "eth_tse_control_port"; 42fb3bbdb8STien Hock Loh clocks = <&sgmii_1_clk_0 &emac1 1 &sgmii_clk_125 &sgmii_clk_125>; 43fb3bbdb8STien Hock Loh clock-names = "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk"; 44fb3bbdb8STien Hock Loh}; 45fb3bbdb8STien Hock Loh 462755e187SDinh Nguyengmac0: ethernet@ff700000 { 472755e187SDinh Nguyen compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; 482755e187SDinh Nguyen altr,sysmgr-syscon = <&sysmgr 0x60 0>; 492755e187SDinh Nguyen reg = <0xff700000 0x2000>; 502755e187SDinh Nguyen interrupts = <0 115 4>; 512755e187SDinh Nguyen interrupt-names = "macirq"; 522755e187SDinh Nguyen mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ 532755e187SDinh Nguyen clocks = <&emac_0_clk>; 54ae107d06SGeert Uytterhoeven clock-names = "stmmaceth"; 55fb3bbdb8STien Hock Loh phy-mode = "sgmii"; 56fb3bbdb8STien Hock Loh altr,gmii-to-sgmii-converter = <&gmii_to_sgmii_converter>; 572755e187SDinh Nguyen}; 58