1*22028070SMason YangMacronix Raw NAND Controller Device Tree Bindings 2*22028070SMason Yang------------------------------------------------- 3*22028070SMason Yang 4*22028070SMason YangRequired properties: 5*22028070SMason Yang- compatible: should be "mxic,multi-itfc-v009-nand-controller" 6*22028070SMason Yang- reg: should contain 1 entry for the registers 7*22028070SMason Yang- #address-cells: should be set to 1 8*22028070SMason Yang- #size-cells: should be set to 0 9*22028070SMason Yang- interrupts: interrupt line connected to this raw NAND controller 10*22028070SMason Yang- clock-names: should contain "ps", "send" and "send_dly" 11*22028070SMason Yang- clocks: should contain 3 phandles for the "ps", "send" and 12*22028070SMason Yang "send_dly" clocks 13*22028070SMason Yang 14*22028070SMason YangChildren nodes: 15*22028070SMason Yang- children nodes represent the available NAND chips. 16*22028070SMason Yang 17*22028070SMason YangSee Documentation/devicetree/bindings/mtd/nand-controller.yaml 18*22028070SMason Yangfor more details on generic bindings. 19*22028070SMason Yang 20*22028070SMason YangExample: 21*22028070SMason Yang 22*22028070SMason Yang nand: nand-controller@43c30000 { 23*22028070SMason Yang compatible = "mxic,multi-itfc-v009-nand-controller"; 24*22028070SMason Yang reg = <0x43c30000 0x10000>; 25*22028070SMason Yang #address-cells = <1>; 26*22028070SMason Yang #size-cells = <0>; 27*22028070SMason Yang interrupts = <GIC_SPI 0x1d IRQ_TYPE_EDGE_RISING>; 28*22028070SMason Yang clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>; 29*22028070SMason Yang clock-names = "send", "send_dly", "ps"; 30*22028070SMason Yang 31*22028070SMason Yang nand@0 { 32*22028070SMason Yang reg = <0>; 33*22028070SMason Yang nand-ecc-mode = "soft"; 34*22028070SMason Yang nand-ecc-algo = "bch"; 35*22028070SMason Yang }; 36*22028070SMason Yang }; 37