xref: /openbmc/linux/Documentation/devicetree/bindings/mmc/sdhci-atmel.txt (revision 5cd41fe89704d4614562363d9051ee8bfdcf1ea1)
1bb5f8ea4Sludovic.desroches@atmel.com* Atmel SDHCI controller
2bb5f8ea4Sludovic.desroches@atmel.com
3bb5f8ea4Sludovic.desroches@atmel.comThis file documents the differences between the core properties in
4bb5f8ea4Sludovic.desroches@atmel.comDocumentation/devicetree/bindings/mmc/mmc.txt and the properties used by the
5bb5f8ea4Sludovic.desroches@atmel.comsdhci-of-at91 driver.
6bb5f8ea4Sludovic.desroches@atmel.com
7bb5f8ea4Sludovic.desroches@atmel.comRequired properties:
8bb5f8ea4Sludovic.desroches@atmel.com- compatible:		Must be "atmel,sama5d2-sdhci".
9bb5f8ea4Sludovic.desroches@atmel.com- clocks:		Phandlers to the clocks.
10bb5f8ea4Sludovic.desroches@atmel.com- clock-names:		Must be "hclock", "multclk", "baseclk";
11bb5f8ea4Sludovic.desroches@atmel.com
12*5cd41fe8SNicolas FerreOptional properties:
13*5cd41fe8SNicolas Ferre- microchip,sdcal-inverted: when present, polarity on the SDCAL SoC pin is
14*5cd41fe8SNicolas Ferre  inverted. The default polarity for this signal is described in the datasheet.
15*5cd41fe8SNicolas Ferre  For instance on SAMA5D2, the pin is usually tied to the GND with a resistor
16*5cd41fe8SNicolas Ferre  and a capacitor (see "SDMMC I/O Calibration" chapter).
17bb5f8ea4Sludovic.desroches@atmel.com
18bb5f8ea4Sludovic.desroches@atmel.comExample:
19bb5f8ea4Sludovic.desroches@atmel.com
20bb5f8ea4Sludovic.desroches@atmel.comsdmmc0: sdio-host@a0000000 {
21bb5f8ea4Sludovic.desroches@atmel.com	compatible = "atmel,sama5d2-sdhci";
22bb5f8ea4Sludovic.desroches@atmel.com	reg = <0xa0000000 0x300>;
23bb5f8ea4Sludovic.desroches@atmel.com	interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
24bb5f8ea4Sludovic.desroches@atmel.com	clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
25bb5f8ea4Sludovic.desroches@atmel.com	clock-names = "hclock", "multclk", "baseclk";
26bb5f8ea4Sludovic.desroches@atmel.com};
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