1*7a7e55f4SAndrew Jeffery# SPDX-License-Identifier: GPL-2.0-or-later 2*7a7e55f4SAndrew Jeffery%YAML 1.2 3*7a7e55f4SAndrew Jeffery--- 4*7a7e55f4SAndrew Jeffery$id: http://devicetree.org/schemas/mmc/aspeed,sdhci.yaml# 5*7a7e55f4SAndrew Jeffery$schema: http://devicetree.org/meta-schemas/core.yaml# 6*7a7e55f4SAndrew Jeffery 7*7a7e55f4SAndrew Jefferytitle: ASPEED SD/SDIO/MMC Controller 8*7a7e55f4SAndrew Jeffery 9*7a7e55f4SAndrew Jefferymaintainers: 10*7a7e55f4SAndrew Jeffery - Andrew Jeffery <andrew@aj.id.au> 11*7a7e55f4SAndrew Jeffery - Ryan Chen <ryanchen.aspeed@gmail.com> 12*7a7e55f4SAndrew Jeffery 13*7a7e55f4SAndrew Jefferydescription: |+ 14*7a7e55f4SAndrew Jeffery The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the SDIO 15*7a7e55f4SAndrew Jeffery Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit data bus if 16*7a7e55f4SAndrew Jeffery only a single slot is enabled. 17*7a7e55f4SAndrew Jeffery 18*7a7e55f4SAndrew Jeffery The two slots are supported by a common configuration area. As the SDHCIs for 19*7a7e55f4SAndrew Jeffery the slots are dependent on the common configuration area, they are described 20*7a7e55f4SAndrew Jeffery as child nodes. 21*7a7e55f4SAndrew Jeffery 22*7a7e55f4SAndrew Jefferyproperties: 23*7a7e55f4SAndrew Jeffery compatible: 24*7a7e55f4SAndrew Jeffery enum: 25*7a7e55f4SAndrew Jeffery - aspeed,ast2400-sd-controller 26*7a7e55f4SAndrew Jeffery - aspeed,ast2500-sd-controller 27*7a7e55f4SAndrew Jeffery - aspeed,ast2600-sd-controller 28*7a7e55f4SAndrew Jeffery reg: 29*7a7e55f4SAndrew Jeffery maxItems: 1 30*7a7e55f4SAndrew Jeffery description: Common configuration registers 31*7a7e55f4SAndrew Jeffery "#address-cells": 32*7a7e55f4SAndrew Jeffery const: 1 33*7a7e55f4SAndrew Jeffery "#size-cells": 34*7a7e55f4SAndrew Jeffery const: 1 35*7a7e55f4SAndrew Jeffery ranges: true 36*7a7e55f4SAndrew Jeffery clocks: 37*7a7e55f4SAndrew Jeffery maxItems: 1 38*7a7e55f4SAndrew Jeffery description: The SD/SDIO controller clock gate 39*7a7e55f4SAndrew Jeffery 40*7a7e55f4SAndrew JefferypatternProperties: 41*7a7e55f4SAndrew Jeffery "^sdhci@[0-9a-f]+$": 42*7a7e55f4SAndrew Jeffery type: object 43*7a7e55f4SAndrew Jeffery allOf: 44*7a7e55f4SAndrew Jeffery - $ref: mmc-controller.yaml 45*7a7e55f4SAndrew Jeffery properties: 46*7a7e55f4SAndrew Jeffery compatible: 47*7a7e55f4SAndrew Jeffery enum: 48*7a7e55f4SAndrew Jeffery - aspeed,ast2400-sdhci 49*7a7e55f4SAndrew Jeffery - aspeed,ast2500-sdhci 50*7a7e55f4SAndrew Jeffery - aspeed,ast2600-sdhci 51*7a7e55f4SAndrew Jeffery reg: 52*7a7e55f4SAndrew Jeffery maxItems: 1 53*7a7e55f4SAndrew Jeffery description: The SDHCI registers 54*7a7e55f4SAndrew Jeffery clocks: 55*7a7e55f4SAndrew Jeffery maxItems: 1 56*7a7e55f4SAndrew Jeffery description: The SD bus clock 57*7a7e55f4SAndrew Jeffery interrupts: 58*7a7e55f4SAndrew Jeffery maxItems: 1 59*7a7e55f4SAndrew Jeffery description: The SD interrupt shared between both slots 60*7a7e55f4SAndrew Jeffery sdhci,auto-cmd12: 61*7a7e55f4SAndrew Jeffery type: boolean 62*7a7e55f4SAndrew Jeffery description: Specifies that controller should use auto CMD12 63*7a7e55f4SAndrew Jeffery required: 64*7a7e55f4SAndrew Jeffery - compatible 65*7a7e55f4SAndrew Jeffery - reg 66*7a7e55f4SAndrew Jeffery - clocks 67*7a7e55f4SAndrew Jeffery - interrupts 68*7a7e55f4SAndrew Jeffery 69*7a7e55f4SAndrew JefferyadditionalProperties: false 70*7a7e55f4SAndrew Jeffery 71*7a7e55f4SAndrew Jefferyrequired: 72*7a7e55f4SAndrew Jeffery - compatible 73*7a7e55f4SAndrew Jeffery - reg 74*7a7e55f4SAndrew Jeffery - "#address-cells" 75*7a7e55f4SAndrew Jeffery - "#size-cells" 76*7a7e55f4SAndrew Jeffery - ranges 77*7a7e55f4SAndrew Jeffery - clocks 78*7a7e55f4SAndrew Jeffery 79*7a7e55f4SAndrew Jefferyexamples: 80*7a7e55f4SAndrew Jeffery - | 81*7a7e55f4SAndrew Jeffery #include <dt-bindings/clock/aspeed-clock.h> 82*7a7e55f4SAndrew Jeffery sdc@1e740000 { 83*7a7e55f4SAndrew Jeffery compatible = "aspeed,ast2500-sd-controller"; 84*7a7e55f4SAndrew Jeffery reg = <0x1e740000 0x100>; 85*7a7e55f4SAndrew Jeffery #address-cells = <1>; 86*7a7e55f4SAndrew Jeffery #size-cells = <1>; 87*7a7e55f4SAndrew Jeffery ranges = <0 0x1e740000 0x10000>; 88*7a7e55f4SAndrew Jeffery clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; 89*7a7e55f4SAndrew Jeffery 90*7a7e55f4SAndrew Jeffery sdhci0: sdhci@100 { 91*7a7e55f4SAndrew Jeffery compatible = "aspeed,ast2500-sdhci"; 92*7a7e55f4SAndrew Jeffery reg = <0x100 0x100>; 93*7a7e55f4SAndrew Jeffery interrupts = <26>; 94*7a7e55f4SAndrew Jeffery sdhci,auto-cmd12; 95*7a7e55f4SAndrew Jeffery clocks = <&syscon ASPEED_CLK_SDIO>; 96*7a7e55f4SAndrew Jeffery }; 97*7a7e55f4SAndrew Jeffery 98*7a7e55f4SAndrew Jeffery sdhci1: sdhci@200 { 99*7a7e55f4SAndrew Jeffery compatible = "aspeed,ast2500-sdhci"; 100*7a7e55f4SAndrew Jeffery reg = <0x200 0x100>; 101*7a7e55f4SAndrew Jeffery interrupts = <26>; 102*7a7e55f4SAndrew Jeffery sdhci,auto-cmd12; 103*7a7e55f4SAndrew Jeffery clocks = <&syscon ASPEED_CLK_SDIO>; 104*7a7e55f4SAndrew Jeffery }; 105*7a7e55f4SAndrew Jeffery }; 106