1*64b139f9SDavid Daney* Cavium Interrupt Bus widget 2*64b139f9SDavid Daney 3*64b139f9SDavid DaneyProperties: 4*64b139f9SDavid Daney- compatible: "cavium,octeon-7130-cib" 5*64b139f9SDavid Daney 6*64b139f9SDavid Daney Compatibility with cn70XX SoCs. 7*64b139f9SDavid Daney 8*64b139f9SDavid Daney- interrupt-controller: This is an interrupt controller. 9*64b139f9SDavid Daney 10*64b139f9SDavid Daney- reg: Two elements consisting of the addresses of the RAW and EN 11*64b139f9SDavid Daney registers of the CIB block 12*64b139f9SDavid Daney 13*64b139f9SDavid Daney- cavium,max-bits: The index (zero based) of the highest numbered bit 14*64b139f9SDavid Daney in the CIB block. 15*64b139f9SDavid Daney 16*64b139f9SDavid Daney- interrupts: The CIU line to which the CIB block is connected. 17*64b139f9SDavid Daney 18*64b139f9SDavid Daney- #interrupt-cells: Must be <2>. The first cell is the bit within the 19*64b139f9SDavid Daney CIB. The second cell specifies the triggering semantics of the 20*64b139f9SDavid Daney line. 21*64b139f9SDavid Daney 22*64b139f9SDavid DaneyExample: 23*64b139f9SDavid Daney 24*64b139f9SDavid Daney interrupt-controller@107000000e000 { 25*64b139f9SDavid Daney compatible = "cavium,octeon-7130-cib"; 26*64b139f9SDavid Daney reg = <0x10700 0x0000e000 0x0 0x8>, /* RAW */ 27*64b139f9SDavid Daney <0x10700 0x0000e100 0x0 0x8>; /* EN */ 28*64b139f9SDavid Daney cavium,max-bits = <23>; 29*64b139f9SDavid Daney 30*64b139f9SDavid Daney interrupt-controller; 31*64b139f9SDavid Daney interrupt-parent = <&ciu>; 32*64b139f9SDavid Daney interrupts = <1 24>; 33*64b139f9SDavid Daney /* Interrupts are specified by two parts: 34*64b139f9SDavid Daney * 1) Bit number in the CIB* registers 35*64b139f9SDavid Daney * 2) Triggering (1 - edge rising 36*64b139f9SDavid Daney * 2 - edge falling 37*64b139f9SDavid Daney * 4 - level active high 38*64b139f9SDavid Daney * 8 - level active low) 39*64b139f9SDavid Daney */ 40*64b139f9SDavid Daney #interrupt-cells = <2>; 41*64b139f9SDavid Daney }; 42