1*a53ffb04SChunyan Zhang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*a53ffb04SChunyan Zhang# Copyright 2022 Unisoc Inc. 3*a53ffb04SChunyan Zhang%YAML 1.2 4*a53ffb04SChunyan Zhang--- 5*a53ffb04SChunyan Zhang$id: http://devicetree.org/schemas/mfd/sprd,ums512-glbreg.yaml# 6*a53ffb04SChunyan Zhang$schema: http://devicetree.org/meta-schemas/core.yaml# 7*a53ffb04SChunyan Zhang 8*a53ffb04SChunyan Zhangtitle: Unisoc System Global Register 9*a53ffb04SChunyan Zhang 10*a53ffb04SChunyan Zhangmaintainers: 11*a53ffb04SChunyan Zhang - Orson Zhai <orsonzhai@gmail.com> 12*a53ffb04SChunyan Zhang - Baolin Wang <baolin.wang7@gmail.com> 13*a53ffb04SChunyan Zhang - Chunyan Zhang <zhang.lyra@gmail.com> 14*a53ffb04SChunyan Zhang 15*a53ffb04SChunyan Zhangdescription: 16*a53ffb04SChunyan Zhang Unisoc system global registers provide register map 17*a53ffb04SChunyan Zhang for clocks and some multimedia modules of the SoC. 18*a53ffb04SChunyan Zhang 19*a53ffb04SChunyan Zhangproperties: 20*a53ffb04SChunyan Zhang compatible: 21*a53ffb04SChunyan Zhang items: 22*a53ffb04SChunyan Zhang - const: sprd,ums512-glbregs 23*a53ffb04SChunyan Zhang - const: syscon 24*a53ffb04SChunyan Zhang - const: simple-mfd 25*a53ffb04SChunyan Zhang 26*a53ffb04SChunyan Zhang "#address-cells": 27*a53ffb04SChunyan Zhang const: 1 28*a53ffb04SChunyan Zhang 29*a53ffb04SChunyan Zhang "#size-cells": 30*a53ffb04SChunyan Zhang const: 1 31*a53ffb04SChunyan Zhang 32*a53ffb04SChunyan Zhang ranges: 33*a53ffb04SChunyan Zhang maxItems: 1 34*a53ffb04SChunyan Zhang 35*a53ffb04SChunyan Zhang reg: 36*a53ffb04SChunyan Zhang maxItems: 1 37*a53ffb04SChunyan Zhang 38*a53ffb04SChunyan ZhangpatternProperties: 39*a53ffb04SChunyan Zhang "^clock-controller@[0-9a-f]+$": 40*a53ffb04SChunyan Zhang type: object 41*a53ffb04SChunyan Zhang $ref: /schemas/clock/sprd,ums512-clk.yaml# 42*a53ffb04SChunyan Zhang description: 43*a53ffb04SChunyan Zhang Clock controller for the SoC clocks. 44*a53ffb04SChunyan Zhang 45*a53ffb04SChunyan Zhangrequired: 46*a53ffb04SChunyan Zhang - compatible 47*a53ffb04SChunyan Zhang - reg 48*a53ffb04SChunyan Zhang 49*a53ffb04SChunyan ZhangadditionalProperties: false 50*a53ffb04SChunyan Zhang 51*a53ffb04SChunyan Zhangexamples: 52*a53ffb04SChunyan Zhang - | 53*a53ffb04SChunyan Zhang ap_apb_regs: syscon@71000000 { 54*a53ffb04SChunyan Zhang compatible = "sprd,ums512-glbregs", "syscon", "simple-mfd"; 55*a53ffb04SChunyan Zhang reg = <0x71000000 0x3000>; 56*a53ffb04SChunyan Zhang #address-cells = <1>; 57*a53ffb04SChunyan Zhang #size-cells = <1>; 58*a53ffb04SChunyan Zhang ranges = <0 0x71000000 0x3000>; 59*a53ffb04SChunyan Zhang 60*a53ffb04SChunyan Zhang clock-controller@0 { 61*a53ffb04SChunyan Zhang compatible = "sprd,ums512-apahb-gate"; 62*a53ffb04SChunyan Zhang reg = <0x0 0x2000>; 63*a53ffb04SChunyan Zhang #clock-cells = <1>; 64*a53ffb04SChunyan Zhang }; 65*a53ffb04SChunyan Zhang }; 66*a53ffb04SChunyan Zhang 67*a53ffb04SChunyan Zhang - | 68*a53ffb04SChunyan Zhang ap_intc5_regs: syscon@32360000 { 69*a53ffb04SChunyan Zhang compatible = "sprd,ums512-glbregs", "syscon", "simple-mfd"; 70*a53ffb04SChunyan Zhang reg = <0x32360000 0x1000>; 71*a53ffb04SChunyan Zhang }; 72