1af287ed0SMaxime Ripard# SPDX-License-Identifier: GPL-2.0 2af287ed0SMaxime Ripard%YAML 1.2 3af287ed0SMaxime Ripard--- 4af287ed0SMaxime Ripard$id: http://devicetree.org/schemas/mfd/allwinner,sun6i-a31-prcm.yaml# 5af287ed0SMaxime Ripard$schema: http://devicetree.org/meta-schemas/core.yaml# 6af287ed0SMaxime Ripard 7dd3cb467SAndrew Lunntitle: Allwinner A31 PRCM 8af287ed0SMaxime Ripard 9af287ed0SMaxime Ripardmaintainers: 10af287ed0SMaxime Ripard - Chen-Yu Tsai <wens@csie.org> 11af287ed0SMaxime Ripard - Maxime Ripard <mripard@kernel.org> 12af287ed0SMaxime Ripard 13af287ed0SMaxime Riparddeprecated: true 14af287ed0SMaxime Ripard 15af287ed0SMaxime Ripardproperties: 16af287ed0SMaxime Ripard compatible: 17af287ed0SMaxime Ripard const: allwinner,sun6i-a31-prcm 18af287ed0SMaxime Ripard 19af287ed0SMaxime Ripard reg: 20af287ed0SMaxime Ripard maxItems: 1 21af287ed0SMaxime Ripard 22af287ed0SMaxime RipardpatternProperties: 23af287ed0SMaxime Ripard "^.*_(clk|rst)$": 24af287ed0SMaxime Ripard type: object 2542839dcaSRob Herring unevaluatedProperties: false 26af287ed0SMaxime Ripard 27af287ed0SMaxime Ripard properties: 28af287ed0SMaxime Ripard compatible: 29af287ed0SMaxime Ripard enum: 30af287ed0SMaxime Ripard - allwinner,sun4i-a10-mod0-clk 31af287ed0SMaxime Ripard - allwinner,sun6i-a31-apb0-clk 32af287ed0SMaxime Ripard - allwinner,sun6i-a31-apb0-gates-clk 33af287ed0SMaxime Ripard - allwinner,sun6i-a31-ar100-clk 34af287ed0SMaxime Ripard - allwinner,sun6i-a31-clock-reset 35af287ed0SMaxime Ripard - fixed-factor-clock 36af287ed0SMaxime Ripard 37*881e367aSRob Herring required: 38*881e367aSRob Herring - compatible 39*881e367aSRob Herring 40af287ed0SMaxime Ripard allOf: 41af287ed0SMaxime Ripard - if: 42af287ed0SMaxime Ripard properties: 43af287ed0SMaxime Ripard compatible: 44af287ed0SMaxime Ripard contains: 4542839dcaSRob Herring const: fixed-factor-clock 4642839dcaSRob Herring 4742839dcaSRob Herring then: 4842839dcaSRob Herring $ref: /schemas/clock/fixed-factor-clock.yaml# 4942839dcaSRob Herring 5042839dcaSRob Herring - if: 5142839dcaSRob Herring properties: 5242839dcaSRob Herring compatible: 5342839dcaSRob Herring contains: 5442839dcaSRob Herring const: allwinner,sun4i-a10-mod0-clk 5542839dcaSRob Herring 5642839dcaSRob Herring then: 5742839dcaSRob Herring properties: 5842839dcaSRob Herring "#clock-cells": 5942839dcaSRob Herring const: 0 6042839dcaSRob Herring 6142839dcaSRob Herring clocks: 6242839dcaSRob Herring maxItems: 2 6342839dcaSRob Herring 6442839dcaSRob Herring clock-output-names: 6542839dcaSRob Herring maxItems: 1 6642839dcaSRob Herring 6742839dcaSRob Herring required: 6842839dcaSRob Herring - "#clock-cells" 6942839dcaSRob Herring - clocks 7042839dcaSRob Herring - clock-output-names 7142839dcaSRob Herring 7242839dcaSRob Herring - if: 7342839dcaSRob Herring properties: 7442839dcaSRob Herring compatible: 7542839dcaSRob Herring contains: 76af287ed0SMaxime Ripard const: allwinner,sun6i-a31-apb0-clk 77af287ed0SMaxime Ripard 78af287ed0SMaxime Ripard then: 79af287ed0SMaxime Ripard properties: 80af287ed0SMaxime Ripard "#clock-cells": 81af287ed0SMaxime Ripard const: 0 82af287ed0SMaxime Ripard 83af287ed0SMaxime Ripard clocks: 84af287ed0SMaxime Ripard maxItems: 1 85af287ed0SMaxime Ripard 86af287ed0SMaxime Ripard clock-output-names: 87af287ed0SMaxime Ripard maxItems: 1 88af287ed0SMaxime Ripard 89af287ed0SMaxime Ripard required: 90af287ed0SMaxime Ripard - "#clock-cells" 91af287ed0SMaxime Ripard - clocks 92af287ed0SMaxime Ripard - clock-output-names 93af287ed0SMaxime Ripard 94af287ed0SMaxime Ripard - if: 95af287ed0SMaxime Ripard properties: 96af287ed0SMaxime Ripard compatible: 97af287ed0SMaxime Ripard contains: 98af287ed0SMaxime Ripard const: allwinner,sun6i-a31-apb0-gates-clk 99af287ed0SMaxime Ripard 100af287ed0SMaxime Ripard then: 101af287ed0SMaxime Ripard properties: 102af287ed0SMaxime Ripard "#clock-cells": 103af287ed0SMaxime Ripard const: 1 104af287ed0SMaxime Ripard description: > 105af287ed0SMaxime Ripard This additional argument passed to that clock is the 106af287ed0SMaxime Ripard offset of the bit controlling this particular gate in 107af287ed0SMaxime Ripard the register. 108af287ed0SMaxime Ripard 109af287ed0SMaxime Ripard clocks: 110af287ed0SMaxime Ripard maxItems: 1 111af287ed0SMaxime Ripard 112af287ed0SMaxime Ripard clock-output-names: 113af287ed0SMaxime Ripard minItems: 1 114af287ed0SMaxime Ripard maxItems: 32 115af287ed0SMaxime Ripard 116af287ed0SMaxime Ripard required: 117af287ed0SMaxime Ripard - "#clock-cells" 118af287ed0SMaxime Ripard - clocks 119af287ed0SMaxime Ripard - clock-output-names 120af287ed0SMaxime Ripard 121af287ed0SMaxime Ripard - if: 122af287ed0SMaxime Ripard properties: 123af287ed0SMaxime Ripard compatible: 124af287ed0SMaxime Ripard contains: 125af287ed0SMaxime Ripard const: allwinner,sun6i-a31-ar100-clk 126af287ed0SMaxime Ripard 127af287ed0SMaxime Ripard then: 128af287ed0SMaxime Ripard properties: 129af287ed0SMaxime Ripard "#clock-cells": 130af287ed0SMaxime Ripard const: 0 131af287ed0SMaxime Ripard 132af287ed0SMaxime Ripard clocks: 133af287ed0SMaxime Ripard maxItems: 4 134af287ed0SMaxime Ripard description: > 135af287ed0SMaxime Ripard The parent order must match the hardware programming 136af287ed0SMaxime Ripard order. 137af287ed0SMaxime Ripard 138af287ed0SMaxime Ripard clock-output-names: 139af287ed0SMaxime Ripard maxItems: 1 140af287ed0SMaxime Ripard 141af287ed0SMaxime Ripard required: 142af287ed0SMaxime Ripard - "#clock-cells" 143af287ed0SMaxime Ripard - clocks 144af287ed0SMaxime Ripard - clock-output-names 145af287ed0SMaxime Ripard 146af287ed0SMaxime Ripard - if: 147af287ed0SMaxime Ripard properties: 148af287ed0SMaxime Ripard compatible: 149af287ed0SMaxime Ripard contains: 150af287ed0SMaxime Ripard const: allwinner,sun6i-a31-clock-reset 151af287ed0SMaxime Ripard 152af287ed0SMaxime Ripard then: 153af287ed0SMaxime Ripard properties: 154af287ed0SMaxime Ripard "#reset-cells": 155af287ed0SMaxime Ripard const: 1 156af287ed0SMaxime Ripard 157af287ed0SMaxime Ripard required: 158af287ed0SMaxime Ripard - "#reset-cells" 159af287ed0SMaxime Ripard 160af287ed0SMaxime Ripardrequired: 161af287ed0SMaxime Ripard - compatible 162af287ed0SMaxime Ripard - reg 163af287ed0SMaxime Ripard 164af287ed0SMaxime RipardadditionalProperties: false 165af287ed0SMaxime Ripard 166af287ed0SMaxime Ripardexamples: 167af287ed0SMaxime Ripard - | 168af287ed0SMaxime Ripard #include <dt-bindings/clock/sun6i-a31-ccu.h> 169af287ed0SMaxime Ripard 170af287ed0SMaxime Ripard prcm@1f01400 { 171af287ed0SMaxime Ripard compatible = "allwinner,sun6i-a31-prcm"; 172af287ed0SMaxime Ripard reg = <0x01f01400 0x200>; 173af287ed0SMaxime Ripard 174af287ed0SMaxime Ripard ar100: ar100_clk { 175af287ed0SMaxime Ripard compatible = "allwinner,sun6i-a31-ar100-clk"; 176af287ed0SMaxime Ripard #clock-cells = <0>; 177af287ed0SMaxime Ripard clocks = <&rtc 0>, <&osc24M>, 178af287ed0SMaxime Ripard <&ccu CLK_PLL_PERIPH>, 179af287ed0SMaxime Ripard <&ccu CLK_PLL_PERIPH>; 180af287ed0SMaxime Ripard clock-output-names = "ar100"; 181af287ed0SMaxime Ripard }; 182af287ed0SMaxime Ripard 183af287ed0SMaxime Ripard ahb0: ahb0_clk { 184af287ed0SMaxime Ripard compatible = "fixed-factor-clock"; 185af287ed0SMaxime Ripard #clock-cells = <0>; 186af287ed0SMaxime Ripard clock-div = <1>; 187af287ed0SMaxime Ripard clock-mult = <1>; 188af287ed0SMaxime Ripard clocks = <&ar100>; 189af287ed0SMaxime Ripard clock-output-names = "ahb0"; 190af287ed0SMaxime Ripard }; 191af287ed0SMaxime Ripard 192af287ed0SMaxime Ripard apb0: apb0_clk { 193af287ed0SMaxime Ripard compatible = "allwinner,sun6i-a31-apb0-clk"; 194af287ed0SMaxime Ripard #clock-cells = <0>; 195af287ed0SMaxime Ripard clocks = <&ahb0>; 196af287ed0SMaxime Ripard clock-output-names = "apb0"; 197af287ed0SMaxime Ripard }; 198af287ed0SMaxime Ripard 199af287ed0SMaxime Ripard apb0_gates: apb0_gates_clk { 200af287ed0SMaxime Ripard compatible = "allwinner,sun6i-a31-apb0-gates-clk"; 201af287ed0SMaxime Ripard #clock-cells = <1>; 202af287ed0SMaxime Ripard clocks = <&apb0>; 203af287ed0SMaxime Ripard clock-output-names = "apb0_pio", "apb0_ir", 204af287ed0SMaxime Ripard "apb0_timer", "apb0_p2wi", 205af287ed0SMaxime Ripard "apb0_uart", "apb0_1wire", 206af287ed0SMaxime Ripard "apb0_i2c"; 207af287ed0SMaxime Ripard }; 208af287ed0SMaxime Ripard 209af287ed0SMaxime Ripard ir_clk: ir_clk { 210af287ed0SMaxime Ripard #clock-cells = <0>; 211af287ed0SMaxime Ripard compatible = "allwinner,sun4i-a10-mod0-clk"; 212af287ed0SMaxime Ripard clocks = <&rtc 0>, <&osc24M>; 213af287ed0SMaxime Ripard clock-output-names = "ir"; 214af287ed0SMaxime Ripard }; 215af287ed0SMaxime Ripard 216af287ed0SMaxime Ripard apb0_rst: apb0_rst { 217af287ed0SMaxime Ripard compatible = "allwinner,sun6i-a31-clock-reset"; 218af287ed0SMaxime Ripard #reset-cells = <1>; 219af287ed0SMaxime Ripard }; 220af287ed0SMaxime Ripard }; 221af287ed0SMaxime Ripard 222af287ed0SMaxime Ripard... 223