xref: /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml (revision c900529f3d9161bfde5cca0754f83b4d3c3e0220)
127bb0e42SYong Wu# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
227bb0e42SYong Wu# Copyright (c) 2020 MediaTek Inc.
327bb0e42SYong Wu%YAML 1.2
427bb0e42SYong Wu---
527bb0e42SYong Wu$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-larb.yaml#
627bb0e42SYong Wu$schema: http://devicetree.org/meta-schemas/core.yaml#
727bb0e42SYong Wu
827bb0e42SYong Wutitle: SMI (Smart Multimedia Interface) Local Arbiter
927bb0e42SYong Wu
1027bb0e42SYong Wumaintainers:
1127bb0e42SYong Wu  - Yong Wu <yong.wu@mediatek.com>
1227bb0e42SYong Wu
1327bb0e42SYong Wudescription: |
1427bb0e42SYong Wu  The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
1527bb0e42SYong Wu
1627bb0e42SYong Wuproperties:
1727bb0e42SYong Wu  compatible:
1827bb0e42SYong Wu    oneOf:
1927bb0e42SYong Wu      - enum:
2027bb0e42SYong Wu          - mediatek,mt2701-smi-larb
2127bb0e42SYong Wu          - mediatek,mt2712-smi-larb
2227bb0e42SYong Wu          - mediatek,mt6779-smi-larb
23a2439405SAngeloGioacchino Del Regno          - mediatek,mt6795-smi-larb
2427bb0e42SYong Wu          - mediatek,mt8167-smi-larb
2527bb0e42SYong Wu          - mediatek,mt8173-smi-larb
2627bb0e42SYong Wu          - mediatek,mt8183-smi-larb
276d86f23cSYong Wu          - mediatek,mt8186-smi-larb
289d9fde47SChengci.Xu          - mediatek,mt8188-smi-larb
2931fc9f87SYong Wu          - mediatek,mt8192-smi-larb
30b01065eeSYong Wu          - mediatek,mt8195-smi-larb
3127bb0e42SYong Wu
3227bb0e42SYong Wu      - description: for mt7623
3327bb0e42SYong Wu        items:
3427bb0e42SYong Wu          - const: mediatek,mt7623-smi-larb
3527bb0e42SYong Wu          - const: mediatek,mt2701-smi-larb
3627bb0e42SYong Wu
374ad9a801SAlexandre Mergnat      - items:
384ad9a801SAlexandre Mergnat          - const: mediatek,mt8365-smi-larb
394ad9a801SAlexandre Mergnat          - const: mediatek,mt8186-smi-larb
404ad9a801SAlexandre Mergnat
4127bb0e42SYong Wu  reg:
4227bb0e42SYong Wu    maxItems: 1
4327bb0e42SYong Wu
4427bb0e42SYong Wu  clocks:
4527bb0e42SYong Wu    description: |
4627bb0e42SYong Wu      apb and smi are mandatory. gals(global async local sync) is optional.
4727bb0e42SYong Wu    minItems: 2
4827bb0e42SYong Wu    items:
4927bb0e42SYong Wu      - description: apb is Advanced Peripheral Bus clock, It's the clock for
5027bb0e42SYong Wu          setting the register.
5127bb0e42SYong Wu      - description: smi is the clock for transfer data and command.
5227bb0e42SYong Wu      - description: the clock for gals.
5327bb0e42SYong Wu
5427bb0e42SYong Wu  clock-names:
5527bb0e42SYong Wu    minItems: 2
5627bb0e42SYong Wu    maxItems: 3
5727bb0e42SYong Wu
5827bb0e42SYong Wu  power-domains:
5927bb0e42SYong Wu    maxItems: 1
6027bb0e42SYong Wu
6127bb0e42SYong Wu  mediatek,smi:
6239bd2b6aSRob Herring    $ref: /schemas/types.yaml#/definitions/phandle
6327bb0e42SYong Wu    description: a phandle to the smi_common node.
6427bb0e42SYong Wu
6527bb0e42SYong Wu  mediatek,larb-id:
6627bb0e42SYong Wu    $ref: /schemas/types.yaml#/definitions/uint32
6727bb0e42SYong Wu    minimum: 0
6827bb0e42SYong Wu    maximum: 31
6927bb0e42SYong Wu    description: the hardware id of this larb. It's only required when this
70*47aab533SBjorn Helgaas      hardware id is not consecutive from its M4U point of view.
7127bb0e42SYong Wu
7227bb0e42SYong Wurequired:
7327bb0e42SYong Wu  - compatible
7427bb0e42SYong Wu  - reg
7527bb0e42SYong Wu  - clocks
7627bb0e42SYong Wu  - clock-names
7727bb0e42SYong Wu  - power-domains
7827bb0e42SYong Wu
7927bb0e42SYong WuallOf:
8027bb0e42SYong Wu  - if:  # HW has gals
8127bb0e42SYong Wu      properties:
8227bb0e42SYong Wu        compatible:
8327bb0e42SYong Wu          enum:
8427bb0e42SYong Wu            - mediatek,mt8183-smi-larb
856d86f23cSYong Wu            - mediatek,mt8186-smi-larb
869d9fde47SChengci.Xu            - mediatek,mt8188-smi-larb
87b01065eeSYong Wu            - mediatek,mt8195-smi-larb
8827bb0e42SYong Wu
8927bb0e42SYong Wu    then:
9027bb0e42SYong Wu      properties:
915bf7fa48SYong Wu        clocks:
92996ebc0eSYong Wu          minItems: 2
9327bb0e42SYong Wu          maxItems: 3
9427bb0e42SYong Wu        clock-names:
95996ebc0eSYong Wu          minItems: 2
9627bb0e42SYong Wu          items:
9727bb0e42SYong Wu            - const: apb
9827bb0e42SYong Wu            - const: smi
9927bb0e42SYong Wu            - const: gals
10027bb0e42SYong Wu
10127bb0e42SYong Wu    else:
10227bb0e42SYong Wu      properties:
1035bf7fa48SYong Wu        clocks:
10427bb0e42SYong Wu          minItems: 2
10527bb0e42SYong Wu          maxItems: 2
10627bb0e42SYong Wu        clock-names:
10727bb0e42SYong Wu          items:
10827bb0e42SYong Wu            - const: apb
10927bb0e42SYong Wu            - const: smi
11027bb0e42SYong Wu
11127bb0e42SYong Wu  - if:
11227bb0e42SYong Wu      properties:
11327bb0e42SYong Wu        compatible:
11427bb0e42SYong Wu          contains:
11527bb0e42SYong Wu            enum:
11627bb0e42SYong Wu              - mediatek,mt2701-smi-larb
11727bb0e42SYong Wu              - mediatek,mt2712-smi-larb
11827bb0e42SYong Wu              - mediatek,mt6779-smi-larb
1196d86f23cSYong Wu              - mediatek,mt8186-smi-larb
1209d9fde47SChengci.Xu              - mediatek,mt8188-smi-larb
12131fc9f87SYong Wu              - mediatek,mt8192-smi-larb
122b01065eeSYong Wu              - mediatek,mt8195-smi-larb
12327bb0e42SYong Wu
12427bb0e42SYong Wu    then:
12527bb0e42SYong Wu      required:
12627bb0e42SYong Wu        - mediatek,larb-id
12727bb0e42SYong Wu
12827bb0e42SYong WuadditionalProperties: false
12927bb0e42SYong Wu
13027bb0e42SYong Wuexamples:
13127bb0e42SYong Wu  - |+
13227bb0e42SYong Wu    #include <dt-bindings/clock/mt8173-clk.h>
13327bb0e42SYong Wu    #include <dt-bindings/power/mt8173-power.h>
13427bb0e42SYong Wu
13527bb0e42SYong Wu    larb1: larb@16010000 {
13627bb0e42SYong Wu      compatible = "mediatek,mt8173-smi-larb";
13727bb0e42SYong Wu      reg = <0x16010000 0x1000>;
13827bb0e42SYong Wu      mediatek,smi = <&smi_common>;
13927bb0e42SYong Wu      power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
14027bb0e42SYong Wu      clocks = <&vdecsys CLK_VDEC_CKEN>,
14127bb0e42SYong Wu               <&vdecsys CLK_VDEC_LARB_CKEN>;
14227bb0e42SYong Wu      clock-names = "apb", "smi";
14327bb0e42SYong Wu    };
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