1*d4fd5a56SMarvin Lin# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*d4fd5a56SMarvin Lin%YAML 1.2 3*d4fd5a56SMarvin Lin--- 4*d4fd5a56SMarvin Lin$id: http://devicetree.org/schemas/media/nuvoton,npcm-vcd.yaml# 5*d4fd5a56SMarvin Lin$schema: http://devicetree.org/meta-schemas/core.yaml# 6*d4fd5a56SMarvin Lin 7*d4fd5a56SMarvin Lintitle: Nuvoton NPCM Video Capture/Differentiation Engine 8*d4fd5a56SMarvin Lin 9*d4fd5a56SMarvin Linmaintainers: 10*d4fd5a56SMarvin Lin - Joseph Liu <kwliu@nuvoton.com> 11*d4fd5a56SMarvin Lin - Marvin Lin <kflin@nuvoton.com> 12*d4fd5a56SMarvin Lin 13*d4fd5a56SMarvin Lindescription: | 14*d4fd5a56SMarvin Lin Video Capture/Differentiation Engine (VCD) present on Nuvoton NPCM SoCs. 15*d4fd5a56SMarvin Lin 16*d4fd5a56SMarvin Linproperties: 17*d4fd5a56SMarvin Lin compatible: 18*d4fd5a56SMarvin Lin enum: 19*d4fd5a56SMarvin Lin - nuvoton,npcm750-vcd 20*d4fd5a56SMarvin Lin - nuvoton,npcm845-vcd 21*d4fd5a56SMarvin Lin 22*d4fd5a56SMarvin Lin reg: 23*d4fd5a56SMarvin Lin maxItems: 1 24*d4fd5a56SMarvin Lin 25*d4fd5a56SMarvin Lin interrupts: 26*d4fd5a56SMarvin Lin maxItems: 1 27*d4fd5a56SMarvin Lin 28*d4fd5a56SMarvin Lin resets: 29*d4fd5a56SMarvin Lin maxItems: 1 30*d4fd5a56SMarvin Lin 31*d4fd5a56SMarvin Lin nuvoton,sysgcr: 32*d4fd5a56SMarvin Lin $ref: /schemas/types.yaml#/definitions/phandle 33*d4fd5a56SMarvin Lin description: phandle to access GCR (Global Control Register) registers. 34*d4fd5a56SMarvin Lin 35*d4fd5a56SMarvin Lin nuvoton,sysgfxi: 36*d4fd5a56SMarvin Lin $ref: /schemas/types.yaml#/definitions/phandle 37*d4fd5a56SMarvin Lin description: phandle to access GFXI (Graphics Core Information) registers. 38*d4fd5a56SMarvin Lin 39*d4fd5a56SMarvin Lin nuvoton,ece: 40*d4fd5a56SMarvin Lin $ref: /schemas/types.yaml#/definitions/phandle 41*d4fd5a56SMarvin Lin description: phandle to access ECE (Encoding Compression Engine) registers. 42*d4fd5a56SMarvin Lin 43*d4fd5a56SMarvin Lin memory-region: 44*d4fd5a56SMarvin Lin maxItems: 1 45*d4fd5a56SMarvin Lin description: 46*d4fd5a56SMarvin Lin CMA pool to use for buffers allocation instead of the default CMA pool. 47*d4fd5a56SMarvin Lin 48*d4fd5a56SMarvin Linrequired: 49*d4fd5a56SMarvin Lin - compatible 50*d4fd5a56SMarvin Lin - reg 51*d4fd5a56SMarvin Lin - interrupts 52*d4fd5a56SMarvin Lin - resets 53*d4fd5a56SMarvin Lin - nuvoton,sysgcr 54*d4fd5a56SMarvin Lin - nuvoton,sysgfxi 55*d4fd5a56SMarvin Lin - nuvoton,ece 56*d4fd5a56SMarvin Lin 57*d4fd5a56SMarvin LinadditionalProperties: false 58*d4fd5a56SMarvin Lin 59*d4fd5a56SMarvin Linexamples: 60*d4fd5a56SMarvin Lin - | 61*d4fd5a56SMarvin Lin #include <dt-bindings/interrupt-controller/arm-gic.h> 62*d4fd5a56SMarvin Lin #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h> 63*d4fd5a56SMarvin Lin 64*d4fd5a56SMarvin Lin vcd: vcd@f0810000 { 65*d4fd5a56SMarvin Lin compatible = "nuvoton,npcm750-vcd"; 66*d4fd5a56SMarvin Lin reg = <0xf0810000 0x10000>; 67*d4fd5a56SMarvin Lin interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 68*d4fd5a56SMarvin Lin resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_VCD>; 69*d4fd5a56SMarvin Lin nuvoton,sysgcr = <&gcr>; 70*d4fd5a56SMarvin Lin nuvoton,sysgfxi = <&gfxi>; 71*d4fd5a56SMarvin Lin nuvoton,ece = <&ece>; 72*d4fd5a56SMarvin Lin }; 73