17b8d3d03SEugen Hristev# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 27b8d3d03SEugen Hristev# Copyright (C) 2021 Microchip Technology, Inc. 37b8d3d03SEugen Hristev%YAML 1.2 47b8d3d03SEugen Hristev--- 57b8d3d03SEugen Hristev$id: http://devicetree.org/schemas/media/microchip,xisc.yaml# 67b8d3d03SEugen Hristev$schema: http://devicetree.org/meta-schemas/core.yaml# 77b8d3d03SEugen Hristev 87b8d3d03SEugen Hristevtitle: Microchip eXtended Image Sensor Controller (XISC) 97b8d3d03SEugen Hristev 107b8d3d03SEugen Hristevmaintainers: 117b8d3d03SEugen Hristev - Eugen Hristev <eugen.hristev@microchip.com> 127b8d3d03SEugen Hristev 137b8d3d03SEugen Hristevdescription: | 147b8d3d03SEugen Hristev The eXtended Image Sensor Controller (XISC) device provides the video input capabilities for the 157b8d3d03SEugen Hristev Microchip AT91 SAM family of devices. 167b8d3d03SEugen Hristev 177b8d3d03SEugen Hristev The XISC has a single internal parallel input that supports RAW Bayer, RGB or YUV video. 187b8d3d03SEugen Hristev The source can be either a demuxer from a CSI2 type of bus, or a simple direct bridge to a 197b8d3d03SEugen Hristev parallel sensor. 207b8d3d03SEugen Hristev 217b8d3d03SEugen Hristev The XISC provides one clock output that is used to clock the demuxer/bridge. 227b8d3d03SEugen Hristev 237b8d3d03SEugen Hristevproperties: 247b8d3d03SEugen Hristev compatible: 257b8d3d03SEugen Hristev const: microchip,sama7g5-isc 267b8d3d03SEugen Hristev 277b8d3d03SEugen Hristev reg: 287b8d3d03SEugen Hristev maxItems: 1 297b8d3d03SEugen Hristev 307b8d3d03SEugen Hristev interrupts: 317b8d3d03SEugen Hristev maxItems: 1 327b8d3d03SEugen Hristev 337b8d3d03SEugen Hristev clocks: 347b8d3d03SEugen Hristev maxItems: 1 357b8d3d03SEugen Hristev 367b8d3d03SEugen Hristev clock-names: 377b8d3d03SEugen Hristev items: 387b8d3d03SEugen Hristev - const: hclock 397b8d3d03SEugen Hristev 407b8d3d03SEugen Hristev '#clock-cells': 417b8d3d03SEugen Hristev const: 0 427b8d3d03SEugen Hristev 437b8d3d03SEugen Hristev clock-output-names: 447b8d3d03SEugen Hristev const: isc-mck 457b8d3d03SEugen Hristev 467b8d3d03SEugen Hristev microchip,mipi-mode: 477b8d3d03SEugen Hristev type: boolean 487b8d3d03SEugen Hristev description: 497b8d3d03SEugen Hristev As the XISC is usually connected to a demux/bridge, the XISC receives 507b8d3d03SEugen Hristev the same type of input, however, it should be aware of the type of 517b8d3d03SEugen Hristev signals received. The mipi-mode enables different internal handling 527b8d3d03SEugen Hristev of the data and clock lines. 537b8d3d03SEugen Hristev 547b8d3d03SEugen Hristev port: 55db60b87eSRob Herring $ref: /schemas/graph.yaml#/$defs/port-base 567b8d3d03SEugen Hristev description: 577b8d3d03SEugen Hristev Input port node, single endpoint describing the input pad. 587b8d3d03SEugen Hristev 597b8d3d03SEugen Hristev properties: 607b8d3d03SEugen Hristev endpoint: 617b8d3d03SEugen Hristev $ref: video-interfaces.yaml# 627b8d3d03SEugen Hristev 637b8d3d03SEugen Hristev properties: 647b8d3d03SEugen Hristev bus-type: 657b8d3d03SEugen Hristev enum: [5, 6] 667b8d3d03SEugen Hristev 677b8d3d03SEugen Hristev remote-endpoint: true 687b8d3d03SEugen Hristev 697b8d3d03SEugen Hristev bus-width: 709d5a3451SEugen Hristev enum: [8, 9, 10, 11, 12, 14] 717b8d3d03SEugen Hristev default: 12 727b8d3d03SEugen Hristev 737b8d3d03SEugen Hristev hsync-active: 747b8d3d03SEugen Hristev enum: [0, 1] 757b8d3d03SEugen Hristev default: 1 767b8d3d03SEugen Hristev 777b8d3d03SEugen Hristev vsync-active: 787b8d3d03SEugen Hristev enum: [0, 1] 797b8d3d03SEugen Hristev default: 1 807b8d3d03SEugen Hristev 817b8d3d03SEugen Hristev pclk-sample: 827b8d3d03SEugen Hristev enum: [0, 1] 837b8d3d03SEugen Hristev default: 1 847b8d3d03SEugen Hristev 857b8d3d03SEugen Hristev required: 867b8d3d03SEugen Hristev - remote-endpoint 877b8d3d03SEugen Hristev - bus-type 887b8d3d03SEugen Hristev 897b8d3d03SEugen Hristev additionalProperties: false 907b8d3d03SEugen Hristev 917b8d3d03SEugen Hristev additionalProperties: false 927b8d3d03SEugen Hristev 937b8d3d03SEugen Hristevrequired: 947b8d3d03SEugen Hristev - compatible 957b8d3d03SEugen Hristev - reg 967b8d3d03SEugen Hristev - clocks 977b8d3d03SEugen Hristev - clock-names 987b8d3d03SEugen Hristev - '#clock-cells' 997b8d3d03SEugen Hristev - clock-output-names 1007b8d3d03SEugen Hristev - port 1017b8d3d03SEugen Hristev 1027b8d3d03SEugen HristevadditionalProperties: false 1037b8d3d03SEugen Hristev 1047b8d3d03SEugen Hristevexamples: 1057b8d3d03SEugen Hristev - | 1067b8d3d03SEugen Hristev #include <dt-bindings/interrupt-controller/arm-gic.h> 1077b8d3d03SEugen Hristev #include <dt-bindings/clock/at91.h> 1087b8d3d03SEugen Hristev #include <dt-bindings/interrupt-controller/irq.h> 109*c4cfd47eSLaurent Pinchart #include <dt-bindings/media/video-interfaces.h> 1107b8d3d03SEugen Hristev 1117b8d3d03SEugen Hristev xisc: xisc@e1408000 { 1127b8d3d03SEugen Hristev compatible = "microchip,sama7g5-isc"; 1137b8d3d03SEugen Hristev reg = <0xe1408000 0x2000>; 1147b8d3d03SEugen Hristev interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1157b8d3d03SEugen Hristev clocks = <&pmc PMC_TYPE_PERIPHERAL 56>; 1167b8d3d03SEugen Hristev clock-names = "hclock"; 1177b8d3d03SEugen Hristev #clock-cells = <0>; 1187b8d3d03SEugen Hristev clock-output-names = "isc-mck"; 1197b8d3d03SEugen Hristev 1207b8d3d03SEugen Hristev port { 1217b8d3d03SEugen Hristev xisc_in: endpoint { 122*c4cfd47eSLaurent Pinchart bus-type = <MEDIA_BUS_TYPE_PARALLEL>; 1237b8d3d03SEugen Hristev remote-endpoint = <&csi2dc_out>; 1247b8d3d03SEugen Hristev hsync-active = <1>; 1257b8d3d03SEugen Hristev vsync-active = <1>; 1267b8d3d03SEugen Hristev bus-width = <12>; 1277b8d3d03SEugen Hristev }; 1287b8d3d03SEugen Hristev }; 1297b8d3d03SEugen Hristev }; 130