1*b391202cSMinghsiu Tsai* Mediatek Media Data Path 2*b391202cSMinghsiu Tsai 3*b391202cSMinghsiu TsaiMedia Data Path is used for scaling and color space conversion. 4*b391202cSMinghsiu Tsai 5*b391202cSMinghsiu TsaiRequired properties (controller (parent) node): 6*b391202cSMinghsiu Tsai- compatible: "mediatek,mt8173-mdp" 7*b391202cSMinghsiu Tsai- mediatek,vpu: the node of video processor unit, see 8*b391202cSMinghsiu Tsai Documentation/devicetree/bindings/media/mediatek-vpu.txt for details. 9*b391202cSMinghsiu Tsai 10*b391202cSMinghsiu TsaiRequired properties (all function blocks, child node): 11*b391202cSMinghsiu Tsai- compatible: Should be one of 12*b391202cSMinghsiu Tsai "mediatek,mt8173-mdp-rdma" - read DMA 13*b391202cSMinghsiu Tsai "mediatek,mt8173-mdp-rsz" - resizer 14*b391202cSMinghsiu Tsai "mediatek,mt8173-mdp-wdma" - write DMA 15*b391202cSMinghsiu Tsai "mediatek,mt8173-mdp-wrot" - write DMA with rotation 16*b391202cSMinghsiu Tsai- reg: Physical base address and length of the function block register space 17*b391202cSMinghsiu Tsai- clocks: device clocks, see 18*b391202cSMinghsiu Tsai Documentation/devicetree/bindings/clock/clock-bindings.txt for details. 19*b391202cSMinghsiu Tsai- power-domains: a phandle to the power domain, see 20*b391202cSMinghsiu Tsai Documentation/devicetree/bindings/power/power_domain.txt for details. 21*b391202cSMinghsiu Tsai 22*b391202cSMinghsiu TsaiRequired properties (DMA function blocks, child node): 23*b391202cSMinghsiu Tsai- compatible: Should be one of 24*b391202cSMinghsiu Tsai "mediatek,mt8173-mdp-rdma" 25*b391202cSMinghsiu Tsai "mediatek,mt8173-mdp-wdma" 26*b391202cSMinghsiu Tsai "mediatek,mt8173-mdp-wrot" 27*b391202cSMinghsiu Tsai- iommus: should point to the respective IOMMU block with master port as 28*b391202cSMinghsiu Tsai argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt 29*b391202cSMinghsiu Tsai for details. 30*b391202cSMinghsiu Tsai- mediatek,larb: must contain the local arbiters in the current Socs, see 31*b391202cSMinghsiu Tsai Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt 32*b391202cSMinghsiu Tsai for details. 33*b391202cSMinghsiu Tsai 34*b391202cSMinghsiu TsaiExample: 35*b391202cSMinghsiu Tsaimdp { 36*b391202cSMinghsiu Tsai compatible = "mediatek,mt8173-mdp"; 37*b391202cSMinghsiu Tsai #address-cells = <2>; 38*b391202cSMinghsiu Tsai #size-cells = <2>; 39*b391202cSMinghsiu Tsai ranges; 40*b391202cSMinghsiu Tsai mediatek,vpu = <&vpu>; 41*b391202cSMinghsiu Tsai 42*b391202cSMinghsiu Tsai mdp_rdma0: rdma@14001000 { 43*b391202cSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rdma"; 44*b391202cSMinghsiu Tsai reg = <0 0x14001000 0 0x1000>; 45*b391202cSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RDMA0>, 46*b391202cSMinghsiu Tsai <&mmsys CLK_MM_MUTEX_32K>; 47*b391202cSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 48*b391202cSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_RDMA0>; 49*b391202cSMinghsiu Tsai mediatek,larb = <&larb0>; 50*b391202cSMinghsiu Tsai }; 51*b391202cSMinghsiu Tsai 52*b391202cSMinghsiu Tsai mdp_rdma1: rdma@14002000 { 53*b391202cSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rdma"; 54*b391202cSMinghsiu Tsai reg = <0 0x14002000 0 0x1000>; 55*b391202cSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RDMA1>, 56*b391202cSMinghsiu Tsai <&mmsys CLK_MM_MUTEX_32K>; 57*b391202cSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 58*b391202cSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_RDMA1>; 59*b391202cSMinghsiu Tsai mediatek,larb = <&larb4>; 60*b391202cSMinghsiu Tsai }; 61*b391202cSMinghsiu Tsai 62*b391202cSMinghsiu Tsai mdp_rsz0: rsz@14003000 { 63*b391202cSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 64*b391202cSMinghsiu Tsai reg = <0 0x14003000 0 0x1000>; 65*b391202cSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ0>; 66*b391202cSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 67*b391202cSMinghsiu Tsai }; 68*b391202cSMinghsiu Tsai 69*b391202cSMinghsiu Tsai mdp_rsz1: rsz@14004000 { 70*b391202cSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 71*b391202cSMinghsiu Tsai reg = <0 0x14004000 0 0x1000>; 72*b391202cSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ1>; 73*b391202cSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 74*b391202cSMinghsiu Tsai }; 75*b391202cSMinghsiu Tsai 76*b391202cSMinghsiu Tsai mdp_rsz2: rsz@14005000 { 77*b391202cSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 78*b391202cSMinghsiu Tsai reg = <0 0x14005000 0 0x1000>; 79*b391202cSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ2>; 80*b391202cSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 81*b391202cSMinghsiu Tsai }; 82*b391202cSMinghsiu Tsai 83*b391202cSMinghsiu Tsai mdp_wdma0: wdma@14006000 { 84*b391202cSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wdma"; 85*b391202cSMinghsiu Tsai reg = <0 0x14006000 0 0x1000>; 86*b391202cSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WDMA>; 87*b391202cSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 88*b391202cSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WDMA>; 89*b391202cSMinghsiu Tsai mediatek,larb = <&larb0>; 90*b391202cSMinghsiu Tsai }; 91*b391202cSMinghsiu Tsai 92*b391202cSMinghsiu Tsai mdp_wrot0: wrot@14007000 { 93*b391202cSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wrot"; 94*b391202cSMinghsiu Tsai reg = <0 0x14007000 0 0x1000>; 95*b391202cSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WROT0>; 96*b391202cSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 97*b391202cSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WROT0>; 98*b391202cSMinghsiu Tsai mediatek,larb = <&larb0>; 99*b391202cSMinghsiu Tsai }; 100*b391202cSMinghsiu Tsai 101*b391202cSMinghsiu Tsai mdp_wrot1: wrot@14008000 { 102*b391202cSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wrot"; 103*b391202cSMinghsiu Tsai reg = <0 0x14008000 0 0x1000>; 104*b391202cSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WROT1>; 105*b391202cSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 106*b391202cSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WROT1>; 107*b391202cSMinghsiu Tsai mediatek,larb = <&larb4>; 108*b391202cSMinghsiu Tsai }; 109*b391202cSMinghsiu Tsai}; 110