1a16ce2f3SHsin-Yi Wang# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2a16ce2f3SHsin-Yi Wang%YAML 1.2 3a16ce2f3SHsin-Yi Wang--- 4a16ce2f3SHsin-Yi Wang$id: http://devicetree.org/schemas/media/mediatek-jpeg-decoder.yaml# 5a16ce2f3SHsin-Yi Wang$schema: http://devicetree.org/meta-schemas/core.yaml# 6a16ce2f3SHsin-Yi Wang 7dd3cb467SAndrew Lunntitle: MediaTek JPEG Decoder 8a16ce2f3SHsin-Yi Wang 9a16ce2f3SHsin-Yi Wangmaintainers: 10a16ce2f3SHsin-Yi Wang - Xia Jiang <xia.jiang@mediatek.com> 11a16ce2f3SHsin-Yi Wang 12a16ce2f3SHsin-Yi Wangdescription: |- 13a16ce2f3SHsin-Yi Wang Mediatek JPEG Decoder is the JPEG decode hardware present in Mediatek SoCs 14a16ce2f3SHsin-Yi Wang 15a16ce2f3SHsin-Yi Wangproperties: 16a16ce2f3SHsin-Yi Wang compatible: 17a16ce2f3SHsin-Yi Wang oneOf: 18a16ce2f3SHsin-Yi Wang - items: 19a16ce2f3SHsin-Yi Wang - enum: 20a16ce2f3SHsin-Yi Wang - mediatek,mt8173-jpgdec 21a16ce2f3SHsin-Yi Wang - mediatek,mt2701-jpgdec 22a16ce2f3SHsin-Yi Wang - items: 23a16ce2f3SHsin-Yi Wang - enum: 24a16ce2f3SHsin-Yi Wang - mediatek,mt7623-jpgdec 25*11edcbb2SJianhua Lin - mediatek,mt8188-jpgdec 26a16ce2f3SHsin-Yi Wang - const: mediatek,mt2701-jpgdec 27a16ce2f3SHsin-Yi Wang 28a16ce2f3SHsin-Yi Wang reg: 29a16ce2f3SHsin-Yi Wang maxItems: 1 30a16ce2f3SHsin-Yi Wang 31a16ce2f3SHsin-Yi Wang interrupts: 32a16ce2f3SHsin-Yi Wang maxItems: 1 33a16ce2f3SHsin-Yi Wang 34a16ce2f3SHsin-Yi Wang clocks: 35a16ce2f3SHsin-Yi Wang maxItems: 2 36a16ce2f3SHsin-Yi Wang minItems: 2 37a16ce2f3SHsin-Yi Wang 38a16ce2f3SHsin-Yi Wang clock-names: 39a16ce2f3SHsin-Yi Wang items: 40a16ce2f3SHsin-Yi Wang - const: jpgdec-smi 41a16ce2f3SHsin-Yi Wang - const: jpgdec 42a16ce2f3SHsin-Yi Wang 43a16ce2f3SHsin-Yi Wang power-domains: 44a16ce2f3SHsin-Yi Wang maxItems: 1 45a16ce2f3SHsin-Yi Wang 46a16ce2f3SHsin-Yi Wang iommus: 47a16ce2f3SHsin-Yi Wang maxItems: 2 48a16ce2f3SHsin-Yi Wang description: | 49a16ce2f3SHsin-Yi Wang Points to the respective IOMMU block with master port as argument, see 50a16ce2f3SHsin-Yi Wang Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. 51a16ce2f3SHsin-Yi Wang Ports are according to the HW. 52a16ce2f3SHsin-Yi Wang 53a16ce2f3SHsin-Yi Wangrequired: 54a16ce2f3SHsin-Yi Wang - compatible 55a16ce2f3SHsin-Yi Wang - reg 56a16ce2f3SHsin-Yi Wang - interrupts 57a16ce2f3SHsin-Yi Wang - clocks 58a16ce2f3SHsin-Yi Wang - clock-names 59a16ce2f3SHsin-Yi Wang - power-domains 60a16ce2f3SHsin-Yi Wang - iommus 61a16ce2f3SHsin-Yi Wang 62a16ce2f3SHsin-Yi WangadditionalProperties: false 63a16ce2f3SHsin-Yi Wang 64a16ce2f3SHsin-Yi Wangexamples: 65a16ce2f3SHsin-Yi Wang - | 66a16ce2f3SHsin-Yi Wang #include <dt-bindings/clock/mt2701-clk.h> 67a16ce2f3SHsin-Yi Wang #include <dt-bindings/interrupt-controller/arm-gic.h> 68a16ce2f3SHsin-Yi Wang #include <dt-bindings/memory/mt2701-larb-port.h> 69a16ce2f3SHsin-Yi Wang #include <dt-bindings/power/mt2701-power.h> 70a16ce2f3SHsin-Yi Wang jpegdec: jpegdec@15004000 { 71a16ce2f3SHsin-Yi Wang compatible = "mediatek,mt2701-jpgdec"; 72a16ce2f3SHsin-Yi Wang reg = <0x15004000 0x1000>; 73a16ce2f3SHsin-Yi Wang interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>; 74a16ce2f3SHsin-Yi Wang clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, 75a16ce2f3SHsin-Yi Wang <&imgsys CLK_IMG_JPGDEC>; 76a16ce2f3SHsin-Yi Wang clock-names = "jpgdec-smi", 77a16ce2f3SHsin-Yi Wang "jpgdec"; 78a16ce2f3SHsin-Yi Wang power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; 79a16ce2f3SHsin-Yi Wang iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, 80a16ce2f3SHsin-Yi Wang <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; 81a16ce2f3SHsin-Yi Wang }; 82