1*331ae5fcSSimon ArlottBroadcom BCM6345-style Level 1 interrupt controller 2*331ae5fcSSimon Arlott 3*331ae5fcSSimon ArlottThis block is a first level interrupt controller that is typically connected 4*331ae5fcSSimon Arlottdirectly to one of the HW INT lines on each CPU. 5*331ae5fcSSimon Arlott 6*331ae5fcSSimon ArlottKey elements of the hardware design include: 7*331ae5fcSSimon Arlott 8*331ae5fcSSimon Arlott- 32, 64 or 128 incoming level IRQ lines 9*331ae5fcSSimon Arlott 10*331ae5fcSSimon Arlott- Most onchip peripherals are wired directly to an L1 input 11*331ae5fcSSimon Arlott 12*331ae5fcSSimon Arlott- A separate instance of the register set for each CPU, allowing individual 13*331ae5fcSSimon Arlott peripheral IRQs to be routed to any CPU 14*331ae5fcSSimon Arlott 15*331ae5fcSSimon Arlott- Contains one or more enable/status word pairs per CPU 16*331ae5fcSSimon Arlott 17*331ae5fcSSimon Arlott- No atomic set/clear operations 18*331ae5fcSSimon Arlott 19*331ae5fcSSimon Arlott- No polarity/level/edge settings 20*331ae5fcSSimon Arlott 21*331ae5fcSSimon Arlott- No FIFO or priority encoder logic; software is expected to read all 22*331ae5fcSSimon Arlott 2-4 status words to determine which IRQs are pending 23*331ae5fcSSimon Arlott 24*331ae5fcSSimon ArlottRequired properties: 25*331ae5fcSSimon Arlott 26*331ae5fcSSimon Arlott- compatible: should be "brcm,bcm<soc>-l1-intc", "brcm,bcm6345-l1-intc" 27*331ae5fcSSimon Arlott- reg: specifies the base physical address and size of the registers; 28*331ae5fcSSimon Arlott the number of supported IRQs is inferred from the size argument 29*331ae5fcSSimon Arlott- interrupt-controller: identifies the node as an interrupt controller 30*331ae5fcSSimon Arlott- #interrupt-cells: specifies the number of cells needed to encode an interrupt 31*331ae5fcSSimon Arlott source, should be 1. 32*331ae5fcSSimon Arlott- interrupts: specifies the interrupt line(s) in the interrupt-parent controller 33*331ae5fcSSimon Arlott node; valid values depend on the type of parent interrupt controller 34*331ae5fcSSimon Arlott 35*331ae5fcSSimon ArlottIf multiple reg ranges and interrupt-parent entries are present on an SMP 36*331ae5fcSSimon Arlottsystem, the driver will allow IRQ SMP affinity to be set up through the 37*331ae5fcSSimon Arlott/proc/irq/ interface. In the simplest possible configuration, only one 38*331ae5fcSSimon Arlottreg range and one interrupt-parent is needed. 39*331ae5fcSSimon Arlott 40*331ae5fcSSimon ArlottThe driver operates in native CPU endian by default, there is no support for 41*331ae5fcSSimon Arlottspecifying an alternative endianness. 42*331ae5fcSSimon Arlott 43*331ae5fcSSimon ArlottExample: 44*331ae5fcSSimon Arlott 45*331ae5fcSSimon Arlottperiph_intc: interrupt-controller@10000000 { 46*331ae5fcSSimon Arlott compatible = "brcm,bcm63168-l1-intc", "brcm,bcm6345-l1-intc"; 47*331ae5fcSSimon Arlott reg = <0x10000020 0x20>, 48*331ae5fcSSimon Arlott <0x10000040 0x20>; 49*331ae5fcSSimon Arlott 50*331ae5fcSSimon Arlott interrupt-controller; 51*331ae5fcSSimon Arlott #interrupt-cells = <1>; 52*331ae5fcSSimon Arlott 53*331ae5fcSSimon Arlott interrupt-parent = <&cpu_intc>; 54*331ae5fcSSimon Arlott interrupts = <2>, <3>; 55*331ae5fcSSimon Arlott}; 56