1*f2b56452SJoshua ClaytonAltera Passive Serial SPI FPGA Manager 2*f2b56452SJoshua Clayton 3*f2b56452SJoshua ClaytonAltera FPGAs support a method of loading the bitstream over what is 4*f2b56452SJoshua Claytonreferred to as "passive serial". 5*f2b56452SJoshua ClaytonThe passive serial link is not technically SPI, and might require extra 6*f2b56452SJoshua Claytoncircuits in order to play nicely with other SPI slaves on the same bus. 7*f2b56452SJoshua Clayton 8*f2b56452SJoshua ClaytonSee https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf 9*f2b56452SJoshua Clayton 10*f2b56452SJoshua ClaytonRequired properties: 11*f2b56452SJoshua Clayton- compatible: Must be one of the following: 12*f2b56452SJoshua Clayton "altr,fpga-passive-serial", 13*f2b56452SJoshua Clayton "altr,fpga-arria10-passive-serial" 14*f2b56452SJoshua Clayton- reg: SPI chip select of the FPGA 15*f2b56452SJoshua Clayton- nconfig-gpios: config pin (referred to as nCONFIG in the manual) 16*f2b56452SJoshua Clayton- nstat-gpios: status pin (referred to as nSTATUS in the manual) 17*f2b56452SJoshua Clayton 18*f2b56452SJoshua ClaytonOptional properties: 19*f2b56452SJoshua Clayton- confd-gpios: confd pin (referred to as CONF_DONE in the manual) 20*f2b56452SJoshua Clayton 21*f2b56452SJoshua ClaytonExample: 22*f2b56452SJoshua Clayton fpga: fpga@0 { 23*f2b56452SJoshua Clayton compatible = "altr,fpga-passive-serial"; 24*f2b56452SJoshua Clayton spi-max-frequency = <20000000>; 25*f2b56452SJoshua Clayton reg = <0>; 26*f2b56452SJoshua Clayton nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; 27*f2b56452SJoshua Clayton nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; 28*f2b56452SJoshua Clayton confd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; 29*f2b56452SJoshua Clayton }; 30