1e3d19244SAlan TullAltera FPGA/HPS Bridge Driver 2e3d19244SAlan Tull 3e3d19244SAlan TullRequired properties: 4e3d19244SAlan Tull- regs : base address and size for AXI bridge module 5e3d19244SAlan Tull- compatible : Should contain one of: 6e3d19244SAlan Tull "altr,socfpga-lwhps2fpga-bridge", 7e3d19244SAlan Tull "altr,socfpga-hps2fpga-bridge", or 8e3d19244SAlan Tull "altr,socfpga-fpga2hps-bridge" 9e3d19244SAlan Tull- resets : Phandle and reset specifier for this bridge's reset 10e3d19244SAlan Tull- clocks : Clocks used by this module. 11e3d19244SAlan Tull 12*2949dc44SMoritz FischerSee Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings. 13e3d19244SAlan Tull 14e3d19244SAlan TullExample: 15e3d19244SAlan Tull fpga_bridge0: fpga-bridge@ff400000 { 16e3d19244SAlan Tull compatible = "altr,socfpga-lwhps2fpga-bridge"; 17e3d19244SAlan Tull reg = <0xff400000 0x100000>; 18e3d19244SAlan Tull resets = <&rst LWHPS2FPGA_RESET>; 19e3d19244SAlan Tull clocks = <&l4_main_clk>; 20e3d19244SAlan Tull bridge-enable = <0>; 21e3d19244SAlan Tull }; 22e3d19244SAlan Tull 23e3d19244SAlan Tull fpga_bridge1: fpga-bridge@ff500000 { 24e3d19244SAlan Tull compatible = "altr,socfpga-hps2fpga-bridge"; 25e3d19244SAlan Tull reg = <0xff500000 0x10000>; 26e3d19244SAlan Tull resets = <&rst HPS2FPGA_RESET>; 27e3d19244SAlan Tull clocks = <&l4_main_clk>; 28e3d19244SAlan Tull bridge-enable = <1>; 29e3d19244SAlan Tull }; 30e3d19244SAlan Tull 31e3d19244SAlan Tull fpga_bridge2: fpga-bridge@ff600000 { 32e3d19244SAlan Tull compatible = "altr,socfpga-fpga2hps-bridge"; 33e3d19244SAlan Tull reg = <0xff600000 0x100000>; 34e3d19244SAlan Tull resets = <&rst FPGA2HPS_RESET>; 35e3d19244SAlan Tull clocks = <&l4_main_clk>; 36e3d19244SAlan Tull }; 37