xref: /openbmc/linux/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml (revision 23fbc87c8ae6f550a2c919370d44fd29cbb568aa)

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/stericsson,dma40.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ST-Ericsson DMA40 DMA Engine

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  "#dma-cells":
    const: 3
    description: |
      The first cell is the unique device channel number as indicated by this
      table for DB8500 which is the only ASIC known to use DMA40:

      0:  SPI controller 0
      1:  SD/MMC controller 0 (unused)
      2:  SD/MMC controller 1 (unused)
      3:  SD/MMC controller 2 (unused)
      4:  I2C port 1
      5:  I2C port 3
      6:  I2C port 2
      7:  I2C port 4
      8:  Synchronous Serial Port SSP0
      9:  Synchronous Serial Port SSP1
      10: Multi-Channel Display Engine MCDE RX
      11: UART port 2
      12: UART port 1
      13: UART port 0
      14: Multirate Serial Port MSP2
      15: I2C port 0
      16: USB OTG in/out endpoints 7 & 15
      17: USB OTG in/out endpoints 6 & 14
      18: USB OTG in/out endpoints 5 & 13
      19: USB OTG in/out endpoints 4 & 12
      20: SLIMbus or HSI channel 0
      21: SLIMbus or HSI channel 1
      22: SLIMbus or HSI channel 2
      23: SLIMbus or HSI channel 3
      24: Multimedia DSP SXA0
      25: Multimedia DSP SXA1
      26: Multimedia DSP SXA2
      27: Multimedia DSP SXA3
      28: SD/MMC controller 2
      29: SD/MMC controller 0
      30: MSP port 1 on DB8500 v1, MSP port 3 on DB8500 v2
      31: MSP port 0 or SLIMbus channel 0
      32: SD/MMC controller 1
      33: SPI controller 2
      34: i2c3 RX2 TX2
      35: SPI controller 1
      36: USB OTG in/out endpoints 3 & 11
      37: USB OTG in/out endpoints 2 & 10
      38: USB OTG in/out endpoints 1 & 9
      39: USB OTG in/out endpoints 8
      40: SPI controller 3
      41: SD/MMC controller 3
      42: SD/MMC controller 4
      43: SD/MMC controller 5
      44: Multimedia DSP SXA4
      45: Multimedia DSP SXA5
      46: SLIMbus channel 8 or Multimedia DSP SXA6
      47: SLIMbus channel 9 or Multimedia DSP SXA7
      48: Crypto Accelerator 1
      49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX
      50: Hash Accelerator 1 TX
      51: memcpy TX (to be used by the DMA driver for memcpy operations)
      52: SLIMbus or HSI channel 4
      53: SLIMbus or HSI channel 5
      54: SLIMbus or HSI channel 6
      55: SLIMbus or HSI channel 7
      56: memcpy (to be used by the DMA driver for memcpy operations)
      57: memcpy (to be used by the DMA driver for memcpy operations)
      58: memcpy (to be used by the DMA driver for memcpy operations)
      59: memcpy (to be used by the DMA driver for memcpy operations)
      60: memcpy (to be used by the DMA driver for memcpy operations)
      61: Crypto Accelerator 0
      62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX
      63: Hash Accelerator 0 TX

      The second cell is the DMA request line number. This is only used when
      a fixed channel is allocated, and indicated by setting bit 3 in the
      flags field (see below).

      The third cell is a 32bit flags bitfield with the following possible
      bits set:
      0x00000001 (bit 0) - mode:
        Logical channel when unset
        Physical channel when set
      0x00000002 (bit 1) - direction:
        Memory to Device when unset
        Device to Memory when set
      0x00000004 (bit 2) - endianness:
        Little endian when unset
        Big endian when set
      0x00000008 (bit 3) - use fixed channel:
        Use automatic channel selection when unset
        Use DMA request line number when set
      0x00000010 (bit 4) - set channel as high priority:
        Normal priority when unset
        High priority when set

  compatible:
    items:
      - const: stericsson,db8500-dma40
      - const: stericsson,dma40

  reg:
    items:
      - description: DMA40 memory base
      - description: LCPA memory base

  reg-names:
    items:
      - const: base
      - const: lcpa

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  memcpy-channels:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description: Array of u32 elements indicating which channels on the DMA
      engine are elegible for memcpy transfers

required:
  - "#dma-cells"
  - compatible
  - reg
  - interrupts
  - clocks
  - memcpy-channels

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/mfd/dbx500-prcmu.h>
    dma-controller@801C0000 {
      compatible = "stericsson,db8500-dma40", "stericsson,dma40";
      reg = <0x801C0000 0x1000>, <0x40010000 0x800>;
      reg-names = "base", "lcpa";
      interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
      #dma-cells = <3>;
      memcpy-channels = <56 57 58 59 60>;
      clocks = <&prcmu_clk PRCMU_DMACLK>;
    };
...