1*b9fb56b6SKunihiko Hayashi# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*b9fb56b6SKunihiko Hayashi%YAML 1.2 3*b9fb56b6SKunihiko Hayashi--- 4*b9fb56b6SKunihiko Hayashi$id: http://devicetree.org/schemas/dma/socionext,uniphier-xdmac.yaml# 5*b9fb56b6SKunihiko Hayashi$schema: http://devicetree.org/meta-schemas/core.yaml# 6*b9fb56b6SKunihiko Hayashi 7*b9fb56b6SKunihiko Hayashititle: Socionext UniPhier external DMA controller 8*b9fb56b6SKunihiko Hayashi 9*b9fb56b6SKunihiko Hayashidescription: | 10*b9fb56b6SKunihiko Hayashi This describes the devicetree bindings for an external DMA engine to perform 11*b9fb56b6SKunihiko Hayashi memory-to-memory or peripheral-to-memory data transfer capable of supporting 12*b9fb56b6SKunihiko Hayashi 16 channels, implemented in Socionext UniPhier SoCs. 13*b9fb56b6SKunihiko Hayashi 14*b9fb56b6SKunihiko Hayashimaintainers: 15*b9fb56b6SKunihiko Hayashi - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> 16*b9fb56b6SKunihiko Hayashi 17*b9fb56b6SKunihiko HayashiallOf: 18*b9fb56b6SKunihiko Hayashi - $ref: "dma-controller.yaml#" 19*b9fb56b6SKunihiko Hayashi 20*b9fb56b6SKunihiko Hayashiproperties: 21*b9fb56b6SKunihiko Hayashi compatible: 22*b9fb56b6SKunihiko Hayashi const: socionext,uniphier-xdmac 23*b9fb56b6SKunihiko Hayashi 24*b9fb56b6SKunihiko Hayashi reg: 25*b9fb56b6SKunihiko Hayashi items: 26*b9fb56b6SKunihiko Hayashi - description: XDMAC base register region (offset and length) 27*b9fb56b6SKunihiko Hayashi - description: XDMAC extension register region (offset and length) 28*b9fb56b6SKunihiko Hayashi 29*b9fb56b6SKunihiko Hayashi interrupts: 30*b9fb56b6SKunihiko Hayashi maxItems: 1 31*b9fb56b6SKunihiko Hayashi 32*b9fb56b6SKunihiko Hayashi "#dma-cells": 33*b9fb56b6SKunihiko Hayashi const: 2 34*b9fb56b6SKunihiko Hayashi description: | 35*b9fb56b6SKunihiko Hayashi DMA request from clients consists of 2 cells: 36*b9fb56b6SKunihiko Hayashi 1. Channel index 37*b9fb56b6SKunihiko Hayashi 2. Transfer request factor number, If no transfer factor, use 0. 38*b9fb56b6SKunihiko Hayashi The number is SoC-specific, and this should be specified with 39*b9fb56b6SKunihiko Hayashi relation to the device to use the DMA controller. 40*b9fb56b6SKunihiko Hayashi 41*b9fb56b6SKunihiko Hayashi dma-channels: 42*b9fb56b6SKunihiko Hayashi minimum: 1 43*b9fb56b6SKunihiko Hayashi maximum: 16 44*b9fb56b6SKunihiko Hayashi 45*b9fb56b6SKunihiko HayashiadditionalProperties: false 46*b9fb56b6SKunihiko Hayashi 47*b9fb56b6SKunihiko Hayashirequired: 48*b9fb56b6SKunihiko Hayashi - compatible 49*b9fb56b6SKunihiko Hayashi - reg 50*b9fb56b6SKunihiko Hayashi - interrupts 51*b9fb56b6SKunihiko Hayashi - "#dma-cells" 52*b9fb56b6SKunihiko Hayashi 53*b9fb56b6SKunihiko Hayashiexamples: 54*b9fb56b6SKunihiko Hayashi - | 55*b9fb56b6SKunihiko Hayashi xdmac: dma-controller@5fc10000 { 56*b9fb56b6SKunihiko Hayashi compatible = "socionext,uniphier-xdmac"; 57*b9fb56b6SKunihiko Hayashi reg = <0x5fc10000 0x1000>, <0x5fc20000 0x800>; 58*b9fb56b6SKunihiko Hayashi interrupts = <0 188 4>; 59*b9fb56b6SKunihiko Hayashi #dma-cells = <2>; 60*b9fb56b6SKunihiko Hayashi dma-channels = <16>; 61*b9fb56b6SKunihiko Hayashi }; 62*b9fb56b6SKunihiko Hayashi 63*b9fb56b6SKunihiko Hayashi... 64