xref: /openbmc/linux/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml (revision 9a87ffc99ec8eb8d35eed7c4f816d75f5cc9662e)
1fa805360SGreen Wan# SPDX-License-Identifier: GPL-2.0
2fa805360SGreen Wan%YAML 1.2
3fa805360SGreen Wan---
4fa805360SGreen Wan$id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml#
5fa805360SGreen Wan$schema: http://devicetree.org/meta-schemas/core.yaml#
6fa805360SGreen Wan
7fa805360SGreen Wantitle: SiFive Unleashed Rev C000 Platform DMA
8fa805360SGreen Wan
9fa805360SGreen Wanmaintainers:
10fa805360SGreen Wan  - Green Wan <green.wan@sifive.com>
11fa805360SGreen Wan  - Palmer Debbelt <palmer@sifive.com>
12fa805360SGreen Wan  - Paul Walmsley <paul.walmsley@sifive.com>
13fa805360SGreen Wan
14fa805360SGreen Wandescription: |
15fa805360SGreen Wan  Platform DMA is a DMA engine of SiFive Unleashed. It supports 4
16fa805360SGreen Wan  channels. Each channel has 2 interrupts. One is for DMA done and
17fa805360SGreen Wan  the other is for DME error.
18fa805360SGreen Wan
19fa805360SGreen Wan  In different SoC, DMA could be attached to different IRQ line.
20fa805360SGreen Wan  DT file need to be changed to meet the difference. For technical
21fa805360SGreen Wan  doc,
22fa805360SGreen Wan
23fa805360SGreen Wan  https://static.dev.sifive.com/FU540-C000-v1.0.pdf
24fa805360SGreen Wan
2509f724e1SKrzysztof KozlowskiallOf:
26*10cafa2dSKrzysztof Kozlowski  - $ref: dma-controller.yaml#
2709f724e1SKrzysztof Kozlowski
28fa805360SGreen Wanproperties:
29fa805360SGreen Wan  compatible:
30fa805360SGreen Wan    items:
3106006ad2SZong Li      - enum:
3206006ad2SZong Li          - sifive,fu540-c000-pdma
3306006ad2SZong Li      - const: sifive,pdma0
3406006ad2SZong Li    description:
3506006ad2SZong Li      Should be "sifive,<chip>-pdma" and "sifive,pdma<version>".
3606006ad2SZong Li      Supported compatible strings are -
3706006ad2SZong Li      "sifive,fu540-c000-pdma" for the SiFive PDMA v0 as integrated onto the
3806006ad2SZong Li      SiFive FU540 chip resp and "sifive,pdma0" for the SiFive PDMA v0 IP block
3906006ad2SZong Li      with no chip integration tweaks.
40fa805360SGreen Wan
41fa805360SGreen Wan  reg:
42fa805360SGreen Wan    maxItems: 1
43fa805360SGreen Wan
44fa805360SGreen Wan  interrupts:
45fa805360SGreen Wan    minItems: 1
46fa805360SGreen Wan    maxItems: 8
47fa805360SGreen Wan
4806006ad2SZong Li  dma-channels:
4906006ad2SZong Li    description: For backwards-compatibility, the default value is 4
5006006ad2SZong Li    minimum: 1
5106006ad2SZong Li    maximum: 4
5206006ad2SZong Li    default: 4
5306006ad2SZong Li
54fa805360SGreen Wan  '#dma-cells':
55fa805360SGreen Wan    const: 1
56fa805360SGreen Wan
57fa805360SGreen Wanrequired:
58fa805360SGreen Wan  - compatible
59fa805360SGreen Wan  - reg
60fa805360SGreen Wan  - interrupts
61fa805360SGreen Wan
6209f724e1SKrzysztof KozlowskiunevaluatedProperties: false
637f464532SRob Herring
64fa805360SGreen Wanexamples:
65fa805360SGreen Wan  - |
6609f724e1SKrzysztof Kozlowski    dma-controller@3000000 {
6706006ad2SZong Li      compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
68fba56184SRob Herring      reg = <0x3000000 0x8000>;
6906006ad2SZong Li      dma-channels = <4>;
70ca1e147cSGeert Uytterhoeven      interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>;
71fa805360SGreen Wan      #dma-cells = <1>;
72fa805360SGreen Wan    };
73fa805360SGreen Wan
74fa805360SGreen Wan...
75