1*afd4df85SAmireddy Mallikarjuna reddy# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*afd4df85SAmireddy Mallikarjuna reddy%YAML 1.2 3*afd4df85SAmireddy Mallikarjuna reddy--- 4*afd4df85SAmireddy Mallikarjuna reddy$id: http://devicetree.org/schemas/dma/intel,ldma.yaml# 5*afd4df85SAmireddy Mallikarjuna reddy$schema: http://devicetree.org/meta-schemas/core.yaml# 6*afd4df85SAmireddy Mallikarjuna reddy 7*afd4df85SAmireddy Mallikarjuna reddytitle: Lightning Mountain centralized DMA controllers. 8*afd4df85SAmireddy Mallikarjuna reddy 9*afd4df85SAmireddy Mallikarjuna reddymaintainers: 10*afd4df85SAmireddy Mallikarjuna reddy - chuanhua.lei@intel.com 11*afd4df85SAmireddy Mallikarjuna reddy - mallikarjunax.reddy@intel.com 12*afd4df85SAmireddy Mallikarjuna reddy 13*afd4df85SAmireddy Mallikarjuna reddyallOf: 14*afd4df85SAmireddy Mallikarjuna reddy - $ref: "dma-controller.yaml#" 15*afd4df85SAmireddy Mallikarjuna reddy 16*afd4df85SAmireddy Mallikarjuna reddyproperties: 17*afd4df85SAmireddy Mallikarjuna reddy compatible: 18*afd4df85SAmireddy Mallikarjuna reddy enum: 19*afd4df85SAmireddy Mallikarjuna reddy - intel,lgm-cdma 20*afd4df85SAmireddy Mallikarjuna reddy - intel,lgm-dma2tx 21*afd4df85SAmireddy Mallikarjuna reddy - intel,lgm-dma1rx 22*afd4df85SAmireddy Mallikarjuna reddy - intel,lgm-dma1tx 23*afd4df85SAmireddy Mallikarjuna reddy - intel,lgm-dma0tx 24*afd4df85SAmireddy Mallikarjuna reddy - intel,lgm-dma3 25*afd4df85SAmireddy Mallikarjuna reddy - intel,lgm-toe-dma30 26*afd4df85SAmireddy Mallikarjuna reddy - intel,lgm-toe-dma31 27*afd4df85SAmireddy Mallikarjuna reddy 28*afd4df85SAmireddy Mallikarjuna reddy reg: 29*afd4df85SAmireddy Mallikarjuna reddy maxItems: 1 30*afd4df85SAmireddy Mallikarjuna reddy 31*afd4df85SAmireddy Mallikarjuna reddy "#dma-cells": 32*afd4df85SAmireddy Mallikarjuna reddy const: 3 33*afd4df85SAmireddy Mallikarjuna reddy description: 34*afd4df85SAmireddy Mallikarjuna reddy The first cell is the peripheral's DMA request line. 35*afd4df85SAmireddy Mallikarjuna reddy The second cell is the peripheral's (port) number corresponding to the channel. 36*afd4df85SAmireddy Mallikarjuna reddy The third cell is the burst length of the channel. 37*afd4df85SAmireddy Mallikarjuna reddy 38*afd4df85SAmireddy Mallikarjuna reddy dma-channels: 39*afd4df85SAmireddy Mallikarjuna reddy minimum: 1 40*afd4df85SAmireddy Mallikarjuna reddy maximum: 16 41*afd4df85SAmireddy Mallikarjuna reddy 42*afd4df85SAmireddy Mallikarjuna reddy dma-channel-mask: 43*afd4df85SAmireddy Mallikarjuna reddy maxItems: 1 44*afd4df85SAmireddy Mallikarjuna reddy 45*afd4df85SAmireddy Mallikarjuna reddy clocks: 46*afd4df85SAmireddy Mallikarjuna reddy maxItems: 1 47*afd4df85SAmireddy Mallikarjuna reddy 48*afd4df85SAmireddy Mallikarjuna reddy resets: 49*afd4df85SAmireddy Mallikarjuna reddy maxItems: 1 50*afd4df85SAmireddy Mallikarjuna reddy 51*afd4df85SAmireddy Mallikarjuna reddy reset-names: 52*afd4df85SAmireddy Mallikarjuna reddy items: 53*afd4df85SAmireddy Mallikarjuna reddy - const: ctrl 54*afd4df85SAmireddy Mallikarjuna reddy 55*afd4df85SAmireddy Mallikarjuna reddy interrupts: 56*afd4df85SAmireddy Mallikarjuna reddy maxItems: 1 57*afd4df85SAmireddy Mallikarjuna reddy 58*afd4df85SAmireddy Mallikarjuna reddy intel,dma-poll-cnt: 59*afd4df85SAmireddy Mallikarjuna reddy $ref: /schemas/types.yaml#definitions/uint32 60*afd4df85SAmireddy Mallikarjuna reddy description: 61*afd4df85SAmireddy Mallikarjuna reddy DMA descriptor polling counter is used to control the poling mechanism 62*afd4df85SAmireddy Mallikarjuna reddy for the descriptor fetching for all channels. 63*afd4df85SAmireddy Mallikarjuna reddy 64*afd4df85SAmireddy Mallikarjuna reddy intel,dma-byte-en: 65*afd4df85SAmireddy Mallikarjuna reddy type: boolean 66*afd4df85SAmireddy Mallikarjuna reddy description: 67*afd4df85SAmireddy Mallikarjuna reddy DMA byte enable is only valid for DMA write(RX). 68*afd4df85SAmireddy Mallikarjuna reddy Byte enable(1) means DMA write will be based on the number of dwords 69*afd4df85SAmireddy Mallikarjuna reddy instead of the whole burst. 70*afd4df85SAmireddy Mallikarjuna reddy 71*afd4df85SAmireddy Mallikarjuna reddy intel,dma-drb: 72*afd4df85SAmireddy Mallikarjuna reddy type: boolean 73*afd4df85SAmireddy Mallikarjuna reddy description: 74*afd4df85SAmireddy Mallikarjuna reddy DMA descriptor read back to make sure data and desc synchronization. 75*afd4df85SAmireddy Mallikarjuna reddy 76*afd4df85SAmireddy Mallikarjuna reddy intel,dma-dburst-wr: 77*afd4df85SAmireddy Mallikarjuna reddy type: boolean 78*afd4df85SAmireddy Mallikarjuna reddy description: 79*afd4df85SAmireddy Mallikarjuna reddy Enable RX dynamic burst write. When it is enabled, the DMA does RX dynamic burst; 80*afd4df85SAmireddy Mallikarjuna reddy if it is disabled, the DMA RX will still support programmable fixed burst size of 2,4,8,16. 81*afd4df85SAmireddy Mallikarjuna reddy It only applies to RX DMA and memcopy DMA. 82*afd4df85SAmireddy Mallikarjuna reddy 83*afd4df85SAmireddy Mallikarjuna reddyrequired: 84*afd4df85SAmireddy Mallikarjuna reddy - compatible 85*afd4df85SAmireddy Mallikarjuna reddy - reg 86*afd4df85SAmireddy Mallikarjuna reddy 87*afd4df85SAmireddy Mallikarjuna reddyadditionalProperties: false 88*afd4df85SAmireddy Mallikarjuna reddy 89*afd4df85SAmireddy Mallikarjuna reddyexamples: 90*afd4df85SAmireddy Mallikarjuna reddy - | 91*afd4df85SAmireddy Mallikarjuna reddy dma0: dma-controller@e0e00000 { 92*afd4df85SAmireddy Mallikarjuna reddy compatible = "intel,lgm-cdma"; 93*afd4df85SAmireddy Mallikarjuna reddy reg = <0xe0e00000 0x1000>; 94*afd4df85SAmireddy Mallikarjuna reddy #dma-cells = <3>; 95*afd4df85SAmireddy Mallikarjuna reddy dma-channels = <16>; 96*afd4df85SAmireddy Mallikarjuna reddy dma-channel-mask = <0xFFFF>; 97*afd4df85SAmireddy Mallikarjuna reddy interrupt-parent = <&ioapic1>; 98*afd4df85SAmireddy Mallikarjuna reddy interrupts = <82 1>; 99*afd4df85SAmireddy Mallikarjuna reddy resets = <&rcu0 0x30 0>; 100*afd4df85SAmireddy Mallikarjuna reddy reset-names = "ctrl"; 101*afd4df85SAmireddy Mallikarjuna reddy clocks = <&cgu0 80>; 102*afd4df85SAmireddy Mallikarjuna reddy intel,dma-poll-cnt = <4>; 103*afd4df85SAmireddy Mallikarjuna reddy intel,dma-byte-en; 104*afd4df85SAmireddy Mallikarjuna reddy intel,dma-drb; 105*afd4df85SAmireddy Mallikarjuna reddy }; 106*afd4df85SAmireddy Mallikarjuna reddy - | 107*afd4df85SAmireddy Mallikarjuna reddy dma3: dma-controller@ec800000 { 108*afd4df85SAmireddy Mallikarjuna reddy compatible = "intel,lgm-dma3"; 109*afd4df85SAmireddy Mallikarjuna reddy reg = <0xec800000 0x1000>; 110*afd4df85SAmireddy Mallikarjuna reddy clocks = <&cgu0 71>; 111*afd4df85SAmireddy Mallikarjuna reddy resets = <&rcu0 0x10 9>; 112*afd4df85SAmireddy Mallikarjuna reddy #dma-cells = <3>; 113*afd4df85SAmireddy Mallikarjuna reddy intel,dma-poll-cnt = <16>; 114*afd4df85SAmireddy Mallikarjuna reddy intel,dma-byte-en; 115*afd4df85SAmireddy Mallikarjuna reddy intel,dma-dburst-wr; 116*afd4df85SAmireddy Mallikarjuna reddy }; 117