1efdbd734SRob HerringTexas Instruments DRA7x Display Subsystem 2efdbd734SRob Herring========================================= 3efdbd734SRob Herring 4efdbd734SRob HerringSee Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic 5efdbd734SRob Herringdescription about OMAP Display Subsystem bindings. 6efdbd734SRob Herring 7efdbd734SRob HerringDSS Core 8efdbd734SRob Herring-------- 9efdbd734SRob Herring 10efdbd734SRob HerringRequired properties: 11efdbd734SRob Herring- compatible: "ti,dra7-dss" 12efdbd734SRob Herring- reg: address and length of the register spaces for 'dss' 13efdbd734SRob Herring- ti,hwmods: "dss_core" 14efdbd734SRob Herring- clocks: handle to fclk 15efdbd734SRob Herring- clock-names: "fck" 16efdbd734SRob Herring- syscon: phandle to control module core syscon node 17efdbd734SRob Herring 18efdbd734SRob HerringOptional properties: 19efdbd734SRob Herring 20efdbd734SRob HerringSome DRA7xx SoCs have one dedicated video PLL, some have two. These properties 21efdbd734SRob Herringcan be used to describe the video PLLs: 22efdbd734SRob Herring 23efdbd734SRob Herring- reg: address and length of the register spaces for 'pll1_clkctrl', 24efdbd734SRob Herring 'pll1', 'pll2_clkctrl', 'pll2' 25efdbd734SRob Herring- clocks: handle to video1 pll clock and video2 pll clock 26efdbd734SRob Herring- clock-names: "video1_clk" and "video2_clk" 27efdbd734SRob Herring 28efdbd734SRob HerringRequired nodes: 29efdbd734SRob Herring- DISPC 30efdbd734SRob Herring 31efdbd734SRob HerringOptional nodes: 32efdbd734SRob Herring- DSS Submodules: HDMI 33efdbd734SRob Herring- Video port for DPI output 34efdbd734SRob Herring 35efdbd734SRob HerringDPI Endpoint required properties: 36efdbd734SRob Herring- data-lines: number of lines used 37efdbd734SRob Herring 38efdbd734SRob Herring 39efdbd734SRob HerringDISPC 40efdbd734SRob Herring----- 41efdbd734SRob Herring 42efdbd734SRob HerringRequired properties: 43efdbd734SRob Herring- compatible: "ti,dra7-dispc" 44efdbd734SRob Herring- reg: address and length of the register space 45efdbd734SRob Herring- ti,hwmods: "dss_dispc" 46efdbd734SRob Herring- interrupts: the DISPC interrupt 47efdbd734SRob Herring- clocks: handle to fclk 48efdbd734SRob Herring- clock-names: "fck" 49efdbd734SRob Herring 50*32fdb624SPeter UjfalusiOptional properties: 51*32fdb624SPeter Ujfalusi- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit 52*32fdb624SPeter Ujfalusi in bytes per second 53*32fdb624SPeter Ujfalusi 54*32fdb624SPeter Ujfalusi 55efdbd734SRob HerringHDMI 56efdbd734SRob Herring---- 57efdbd734SRob Herring 58efdbd734SRob HerringRequired properties: 59efdbd734SRob Herring- compatible: "ti,dra7-hdmi" 60efdbd734SRob Herring- reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy', 61efdbd734SRob Herring 'core' 62efdbd734SRob Herring- reg-names: "wp", "pll", "phy", "core" 63efdbd734SRob Herring- interrupts: the HDMI interrupt line 64efdbd734SRob Herring- ti,hwmods: "dss_hdmi" 65efdbd734SRob Herring- vdda-supply: vdda power supply 66efdbd734SRob Herring- clocks: handles to fclk and pll clock 67efdbd734SRob Herring- clock-names: "fck", "sys_clk" 68efdbd734SRob Herring 69efdbd734SRob HerringOptional nodes: 70efdbd734SRob Herring- Video port for HDMI output 71efdbd734SRob Herring 72efdbd734SRob HerringHDMI Endpoint optional properties: 73efdbd734SRob Herring- lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-, 74efdbd734SRob Herring D1+, D1-, D2+, D2-. (default: 0,1,2,3,4,5,6,7) 75