xref: /openbmc/linux/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml (revision 98878d9dfc7acbad56c3433f4166472fee56884f)
12d8730f1SJyri Sarha# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
22d8730f1SJyri Sarha# Copyright 2019 Texas Instruments Incorporated
32d8730f1SJyri Sarha%YAML 1.2
42d8730f1SJyri Sarha---
52d8730f1SJyri Sarha$id: "http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#"
62d8730f1SJyri Sarha$schema: "http://devicetree.org/meta-schemas/core.yaml#"
72d8730f1SJyri Sarha
82d8730f1SJyri Sarhatitle: Texas Instruments AM65x Display Subsystem
92d8730f1SJyri Sarha
102d8730f1SJyri Sarhamaintainers:
112d8730f1SJyri Sarha  - Jyri Sarha <jsarha@ti.com>
122d8730f1SJyri Sarha  - Tomi Valkeinen <tomi.valkeinen@ti.com>
132d8730f1SJyri Sarha
142d8730f1SJyri Sarhadescription: |
152d8730f1SJyri Sarha  The AM65x TI Keystone Display SubSystem with two output ports and
162d8730f1SJyri Sarha  two video planes. The first video port supports OLDI and the second
172d8730f1SJyri Sarha  supports DPI format. The fist plane is full video plane with all
182d8730f1SJyri Sarha  features and the second is a "lite plane" without scaling support.
192d8730f1SJyri Sarha
202d8730f1SJyri Sarhaproperties:
212d8730f1SJyri Sarha  compatible:
222d8730f1SJyri Sarha    const: ti,am65x-dss
232d8730f1SJyri Sarha
242d8730f1SJyri Sarha  reg:
252d8730f1SJyri Sarha    description:
262d8730f1SJyri Sarha      Addresses to each DSS memory region described in the SoC's TRM.
272d8730f1SJyri Sarha    items:
282d8730f1SJyri Sarha      - description: common DSS register area
292d8730f1SJyri Sarha      - description: VIDL1 light video plane
302d8730f1SJyri Sarha      - description: VID video plane
312d8730f1SJyri Sarha      - description: OVR1 overlay manager for vp1
322d8730f1SJyri Sarha      - description: OVR2 overlay manager for vp2
332d8730f1SJyri Sarha      - description: VP1 video port 1
342d8730f1SJyri Sarha      - description: VP2 video port 2
352d8730f1SJyri Sarha
362d8730f1SJyri Sarha  reg-names:
372d8730f1SJyri Sarha    items:
382d8730f1SJyri Sarha      - const: common
392d8730f1SJyri Sarha      - const: vidl1
402d8730f1SJyri Sarha      - const: vid
412d8730f1SJyri Sarha      - const: ovr1
422d8730f1SJyri Sarha      - const: ovr2
432d8730f1SJyri Sarha      - const: vp1
442d8730f1SJyri Sarha      - const: vp2
452d8730f1SJyri Sarha
462d8730f1SJyri Sarha  clocks:
472d8730f1SJyri Sarha    items:
482d8730f1SJyri Sarha      - description: fck DSS functional clock
492d8730f1SJyri Sarha      - description: vp1 Video Port 1 pixel clock
502d8730f1SJyri Sarha      - description: vp2 Video Port 2 pixel clock
512d8730f1SJyri Sarha
522d8730f1SJyri Sarha  clock-names:
532d8730f1SJyri Sarha    items:
542d8730f1SJyri Sarha      - const: fck
552d8730f1SJyri Sarha      - const: vp1
562d8730f1SJyri Sarha      - const: vp2
572d8730f1SJyri Sarha
582d8730f1SJyri Sarha  interrupts:
592d8730f1SJyri Sarha    maxItems: 1
602d8730f1SJyri Sarha
612d8730f1SJyri Sarha  power-domains:
622d8730f1SJyri Sarha    maxItems: 1
632d8730f1SJyri Sarha    description: phandle to the associated power domain
642d8730f1SJyri Sarha
652d8730f1SJyri Sarha  ports:
662d8730f1SJyri Sarha    type: object
672d8730f1SJyri Sarha    description:
682d8730f1SJyri Sarha      Ports as described in Documentation/devictree/bindings/graph.txt
692d8730f1SJyri Sarha    properties:
702d8730f1SJyri Sarha      "#address-cells":
712d8730f1SJyri Sarha        const: 1
722d8730f1SJyri Sarha
732d8730f1SJyri Sarha      "#size-cells":
742d8730f1SJyri Sarha        const: 0
752d8730f1SJyri Sarha
762d8730f1SJyri Sarha      port@0:
772d8730f1SJyri Sarha        type: object
782d8730f1SJyri Sarha        description:
792d8730f1SJyri Sarha          The DSS OLDI output port node form video port 1
802d8730f1SJyri Sarha
812d8730f1SJyri Sarha      port@1:
822d8730f1SJyri Sarha        type: object
832d8730f1SJyri Sarha        description:
842d8730f1SJyri Sarha          The DSS DPI output port node from video port 2
852d8730f1SJyri Sarha
862d8730f1SJyri Sarha    required:
872d8730f1SJyri Sarha      - "#address-cells"
882d8730f1SJyri Sarha      - "#size-cells"
892d8730f1SJyri Sarha
902d8730f1SJyri Sarha  ti,am65x-oldi-io-ctrl:
912d8730f1SJyri Sarha    allOf:
922d8730f1SJyri Sarha      - $ref: "/schemas/types.yaml#/definitions/phandle-array"
932d8730f1SJyri Sarha      - maxItems: 1
942d8730f1SJyri Sarha    description:
952d8730f1SJyri Sarha      phandle to syscon device node mapping OLDI IO_CTRL registers.
962d8730f1SJyri Sarha      The mapped range should point to OLDI_DAT0_IO_CTRL, map it and
972d8730f1SJyri Sarha      following OLDI_DAT1_IO_CTRL, OLDI_DAT2_IO_CTRL, OLDI_DAT3_IO_CTRL,
982d8730f1SJyri Sarha      and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI
992d8730f1SJyri Sarha      interface to work.
1002d8730f1SJyri Sarha
1012d8730f1SJyri Sarha  max-memory-bandwidth:
1022d8730f1SJyri Sarha    $ref: /schemas/types.yaml#/definitions/uint32
1032d8730f1SJyri Sarha    description:
1042d8730f1SJyri Sarha      Input memory (from main memory to dispc) bandwidth limit in
1052d8730f1SJyri Sarha      bytes per second
1062d8730f1SJyri Sarha
1072d8730f1SJyri Sarharequired:
1082d8730f1SJyri Sarha  - compatible
1092d8730f1SJyri Sarha  - reg
1102d8730f1SJyri Sarha  - reg-names
1112d8730f1SJyri Sarha  - clocks
1122d8730f1SJyri Sarha  - clock-names
1132d8730f1SJyri Sarha  - interrupts
1142d8730f1SJyri Sarha  - ports
1152d8730f1SJyri Sarha
1162d8730f1SJyri SarhaadditionalProperties: false
1172d8730f1SJyri Sarha
1182d8730f1SJyri Sarhaexamples:
1192d8730f1SJyri Sarha  - |
1202d8730f1SJyri Sarha    #include <dt-bindings/interrupt-controller/arm-gic.h>
1212d8730f1SJyri Sarha    #include <dt-bindings/interrupt-controller/irq.h>
1222d8730f1SJyri Sarha    #include <dt-bindings/soc/ti,sci_pm_domain.h>
1232d8730f1SJyri Sarha
124*98878d9dSRob Herring    dss: dss@4a00000 {
1252d8730f1SJyri Sarha            compatible = "ti,am65x-dss";
1262d8730f1SJyri Sarha            reg =   <0x0 0x04a00000 0x0 0x1000>, /* common */
1272d8730f1SJyri Sarha                    <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
1282d8730f1SJyri Sarha                    <0x0 0x04a06000 0x0 0x1000>, /* vid */
1292d8730f1SJyri Sarha                    <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
1302d8730f1SJyri Sarha                    <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
1312d8730f1SJyri Sarha                    <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
1322d8730f1SJyri Sarha                    <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
1332d8730f1SJyri Sarha            reg-names = "common", "vidl1", "vid",
1342d8730f1SJyri Sarha                    "ovr1", "ovr2", "vp1", "vp2";
1352d8730f1SJyri Sarha            ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
1362d8730f1SJyri Sarha            power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
1372d8730f1SJyri Sarha            clocks =        <&k3_clks 67 1>,
1382d8730f1SJyri Sarha                            <&k3_clks 216 1>,
1392d8730f1SJyri Sarha                            <&k3_clks 67 2>;
1402d8730f1SJyri Sarha            clock-names = "fck", "vp1", "vp2";
1412d8730f1SJyri Sarha            interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
1422d8730f1SJyri Sarha            ports {
1432d8730f1SJyri Sarha                    #address-cells = <1>;
1442d8730f1SJyri Sarha                    #size-cells = <0>;
1452d8730f1SJyri Sarha                    port@0 {
1462d8730f1SJyri Sarha                            reg = <0>;
1472d8730f1SJyri Sarha                            oldi_out0: endpoint {
1482d8730f1SJyri Sarha                                    remote-endpoint = <&lcd_in0>;
1492d8730f1SJyri Sarha                            };
1502d8730f1SJyri Sarha                    };
1512d8730f1SJyri Sarha            };
1522d8730f1SJyri Sarha    };
153