12d8730f1SJyri Sarha# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 22d8730f1SJyri Sarha# Copyright 2019 Texas Instruments Incorporated 32d8730f1SJyri Sarha%YAML 1.2 42d8730f1SJyri Sarha--- 5*4334aec0SRob Herring$id: http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml# 6*4334aec0SRob Herring$schema: http://devicetree.org/meta-schemas/core.yaml# 72d8730f1SJyri Sarha 82d8730f1SJyri Sarhatitle: Texas Instruments AM65x Display Subsystem 92d8730f1SJyri Sarha 102d8730f1SJyri Sarhamaintainers: 112d8730f1SJyri Sarha - Jyri Sarha <jsarha@ti.com> 122d8730f1SJyri Sarha - Tomi Valkeinen <tomi.valkeinen@ti.com> 132d8730f1SJyri Sarha 142d8730f1SJyri Sarhadescription: | 152d8730f1SJyri Sarha The AM65x TI Keystone Display SubSystem with two output ports and 162d8730f1SJyri Sarha two video planes. The first video port supports OLDI and the second 172d8730f1SJyri Sarha supports DPI format. The fist plane is full video plane with all 182d8730f1SJyri Sarha features and the second is a "lite plane" without scaling support. 192d8730f1SJyri Sarha 202d8730f1SJyri Sarhaproperties: 212d8730f1SJyri Sarha compatible: 222d8730f1SJyri Sarha const: ti,am65x-dss 232d8730f1SJyri Sarha 242d8730f1SJyri Sarha reg: 252d8730f1SJyri Sarha description: 262d8730f1SJyri Sarha Addresses to each DSS memory region described in the SoC's TRM. 272d8730f1SJyri Sarha items: 282d8730f1SJyri Sarha - description: common DSS register area 292d8730f1SJyri Sarha - description: VIDL1 light video plane 302d8730f1SJyri Sarha - description: VID video plane 312d8730f1SJyri Sarha - description: OVR1 overlay manager for vp1 322d8730f1SJyri Sarha - description: OVR2 overlay manager for vp2 332d8730f1SJyri Sarha - description: VP1 video port 1 342d8730f1SJyri Sarha - description: VP2 video port 2 352d8730f1SJyri Sarha 362d8730f1SJyri Sarha reg-names: 372d8730f1SJyri Sarha items: 382d8730f1SJyri Sarha - const: common 392d8730f1SJyri Sarha - const: vidl1 402d8730f1SJyri Sarha - const: vid 412d8730f1SJyri Sarha - const: ovr1 422d8730f1SJyri Sarha - const: ovr2 432d8730f1SJyri Sarha - const: vp1 442d8730f1SJyri Sarha - const: vp2 452d8730f1SJyri Sarha 462d8730f1SJyri Sarha clocks: 472d8730f1SJyri Sarha items: 482d8730f1SJyri Sarha - description: fck DSS functional clock 492d8730f1SJyri Sarha - description: vp1 Video Port 1 pixel clock 502d8730f1SJyri Sarha - description: vp2 Video Port 2 pixel clock 512d8730f1SJyri Sarha 522d8730f1SJyri Sarha clock-names: 532d8730f1SJyri Sarha items: 542d8730f1SJyri Sarha - const: fck 552d8730f1SJyri Sarha - const: vp1 562d8730f1SJyri Sarha - const: vp2 572d8730f1SJyri Sarha 586468f234STomi Valkeinen assigned-clocks: 596468f234STomi Valkeinen minItems: 1 606468f234STomi Valkeinen maxItems: 3 616468f234STomi Valkeinen 626468f234STomi Valkeinen assigned-clock-parents: 636468f234STomi Valkeinen minItems: 1 646468f234STomi Valkeinen maxItems: 3 656468f234STomi Valkeinen 662d8730f1SJyri Sarha interrupts: 672d8730f1SJyri Sarha maxItems: 1 682d8730f1SJyri Sarha 692d8730f1SJyri Sarha power-domains: 702d8730f1SJyri Sarha maxItems: 1 712d8730f1SJyri Sarha description: phandle to the associated power domain 722d8730f1SJyri Sarha 736468f234STomi Valkeinen dma-coherent: 746468f234STomi Valkeinen type: boolean 756468f234STomi Valkeinen 762d8730f1SJyri Sarha ports: 77b6755423SRob Herring $ref: /schemas/graph.yaml#/properties/ports 78b6755423SRob Herring 792d8730f1SJyri Sarha properties: 802d8730f1SJyri Sarha port@0: 81b6755423SRob Herring $ref: /schemas/graph.yaml#/properties/port 822d8730f1SJyri Sarha description: 832d8730f1SJyri Sarha The DSS OLDI output port node form video port 1 842d8730f1SJyri Sarha 852d8730f1SJyri Sarha port@1: 86b6755423SRob Herring $ref: /schemas/graph.yaml#/properties/port 872d8730f1SJyri Sarha description: 882d8730f1SJyri Sarha The DSS DPI output port node from video port 2 892d8730f1SJyri Sarha 902d8730f1SJyri Sarha ti,am65x-oldi-io-ctrl: 91*4334aec0SRob Herring $ref: /schemas/types.yaml#/definitions/phandle 922d8730f1SJyri Sarha description: 932d8730f1SJyri Sarha phandle to syscon device node mapping OLDI IO_CTRL registers. 942d8730f1SJyri Sarha The mapped range should point to OLDI_DAT0_IO_CTRL, map it and 952d8730f1SJyri Sarha following OLDI_DAT1_IO_CTRL, OLDI_DAT2_IO_CTRL, OLDI_DAT3_IO_CTRL, 962d8730f1SJyri Sarha and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI 972d8730f1SJyri Sarha interface to work. 982d8730f1SJyri Sarha 992d8730f1SJyri Sarha max-memory-bandwidth: 1002d8730f1SJyri Sarha $ref: /schemas/types.yaml#/definitions/uint32 1012d8730f1SJyri Sarha description: 1022d8730f1SJyri Sarha Input memory (from main memory to dispc) bandwidth limit in 1032d8730f1SJyri Sarha bytes per second 1042d8730f1SJyri Sarha 1052d8730f1SJyri Sarharequired: 1062d8730f1SJyri Sarha - compatible 1072d8730f1SJyri Sarha - reg 1082d8730f1SJyri Sarha - reg-names 1092d8730f1SJyri Sarha - clocks 1102d8730f1SJyri Sarha - clock-names 1112d8730f1SJyri Sarha - interrupts 1122d8730f1SJyri Sarha - ports 1132d8730f1SJyri Sarha 1142d8730f1SJyri SarhaadditionalProperties: false 1152d8730f1SJyri Sarha 1162d8730f1SJyri Sarhaexamples: 1172d8730f1SJyri Sarha - | 1182d8730f1SJyri Sarha #include <dt-bindings/interrupt-controller/arm-gic.h> 1192d8730f1SJyri Sarha #include <dt-bindings/interrupt-controller/irq.h> 1202d8730f1SJyri Sarha #include <dt-bindings/soc/ti,sci_pm_domain.h> 1212d8730f1SJyri Sarha 12298878d9dSRob Herring dss: dss@4a00000 { 1232d8730f1SJyri Sarha compatible = "ti,am65x-dss"; 124fba56184SRob Herring reg = <0x04a00000 0x1000>, /* common */ 125fba56184SRob Herring <0x04a02000 0x1000>, /* vidl1 */ 126fba56184SRob Herring <0x04a06000 0x1000>, /* vid */ 127fba56184SRob Herring <0x04a07000 0x1000>, /* ovr1 */ 128fba56184SRob Herring <0x04a08000 0x1000>, /* ovr2 */ 129fba56184SRob Herring <0x04a0a000 0x1000>, /* vp1 */ 130fba56184SRob Herring <0x04a0b000 0x1000>; /* vp2 */ 1312d8730f1SJyri Sarha reg-names = "common", "vidl1", "vid", 1322d8730f1SJyri Sarha "ovr1", "ovr2", "vp1", "vp2"; 1332d8730f1SJyri Sarha ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; 1342d8730f1SJyri Sarha power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 1352d8730f1SJyri Sarha clocks = <&k3_clks 67 1>, 1362d8730f1SJyri Sarha <&k3_clks 216 1>, 1372d8730f1SJyri Sarha <&k3_clks 67 2>; 1382d8730f1SJyri Sarha clock-names = "fck", "vp1", "vp2"; 1392d8730f1SJyri Sarha interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>; 1402d8730f1SJyri Sarha ports { 1412d8730f1SJyri Sarha #address-cells = <1>; 1422d8730f1SJyri Sarha #size-cells = <0>; 1432d8730f1SJyri Sarha port@0 { 1442d8730f1SJyri Sarha reg = <0>; 1452d8730f1SJyri Sarha oldi_out0: endpoint { 1462d8730f1SJyri Sarha remote-endpoint = <&lcd_in0>; 1472d8730f1SJyri Sarha }; 1482d8730f1SJyri Sarha }; 1492d8730f1SJyri Sarha }; 1502d8730f1SJyri Sarha }; 151