1*2d8730f1SJyri Sarha# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*2d8730f1SJyri Sarha# Copyright 2019 Texas Instruments Incorporated 3*2d8730f1SJyri Sarha%YAML 1.2 4*2d8730f1SJyri Sarha--- 5*2d8730f1SJyri Sarha$id: "http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#" 6*2d8730f1SJyri Sarha$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7*2d8730f1SJyri Sarha 8*2d8730f1SJyri Sarhatitle: Texas Instruments AM65x Display Subsystem 9*2d8730f1SJyri Sarha 10*2d8730f1SJyri Sarhamaintainers: 11*2d8730f1SJyri Sarha - Jyri Sarha <jsarha@ti.com> 12*2d8730f1SJyri Sarha - Tomi Valkeinen <tomi.valkeinen@ti.com> 13*2d8730f1SJyri Sarha 14*2d8730f1SJyri Sarhadescription: | 15*2d8730f1SJyri Sarha The AM65x TI Keystone Display SubSystem with two output ports and 16*2d8730f1SJyri Sarha two video planes. The first video port supports OLDI and the second 17*2d8730f1SJyri Sarha supports DPI format. The fist plane is full video plane with all 18*2d8730f1SJyri Sarha features and the second is a "lite plane" without scaling support. 19*2d8730f1SJyri Sarha 20*2d8730f1SJyri Sarhaproperties: 21*2d8730f1SJyri Sarha compatible: 22*2d8730f1SJyri Sarha const: ti,am65x-dss 23*2d8730f1SJyri Sarha 24*2d8730f1SJyri Sarha reg: 25*2d8730f1SJyri Sarha description: 26*2d8730f1SJyri Sarha Addresses to each DSS memory region described in the SoC's TRM. 27*2d8730f1SJyri Sarha items: 28*2d8730f1SJyri Sarha - description: common DSS register area 29*2d8730f1SJyri Sarha - description: VIDL1 light video plane 30*2d8730f1SJyri Sarha - description: VID video plane 31*2d8730f1SJyri Sarha - description: OVR1 overlay manager for vp1 32*2d8730f1SJyri Sarha - description: OVR2 overlay manager for vp2 33*2d8730f1SJyri Sarha - description: VP1 video port 1 34*2d8730f1SJyri Sarha - description: VP2 video port 2 35*2d8730f1SJyri Sarha 36*2d8730f1SJyri Sarha reg-names: 37*2d8730f1SJyri Sarha items: 38*2d8730f1SJyri Sarha - const: common 39*2d8730f1SJyri Sarha - const: vidl1 40*2d8730f1SJyri Sarha - const: vid 41*2d8730f1SJyri Sarha - const: ovr1 42*2d8730f1SJyri Sarha - const: ovr2 43*2d8730f1SJyri Sarha - const: vp1 44*2d8730f1SJyri Sarha - const: vp2 45*2d8730f1SJyri Sarha 46*2d8730f1SJyri Sarha clocks: 47*2d8730f1SJyri Sarha items: 48*2d8730f1SJyri Sarha - description: fck DSS functional clock 49*2d8730f1SJyri Sarha - description: vp1 Video Port 1 pixel clock 50*2d8730f1SJyri Sarha - description: vp2 Video Port 2 pixel clock 51*2d8730f1SJyri Sarha 52*2d8730f1SJyri Sarha clock-names: 53*2d8730f1SJyri Sarha items: 54*2d8730f1SJyri Sarha - const: fck 55*2d8730f1SJyri Sarha - const: vp1 56*2d8730f1SJyri Sarha - const: vp2 57*2d8730f1SJyri Sarha 58*2d8730f1SJyri Sarha interrupts: 59*2d8730f1SJyri Sarha maxItems: 1 60*2d8730f1SJyri Sarha 61*2d8730f1SJyri Sarha power-domains: 62*2d8730f1SJyri Sarha maxItems: 1 63*2d8730f1SJyri Sarha description: phandle to the associated power domain 64*2d8730f1SJyri Sarha 65*2d8730f1SJyri Sarha ports: 66*2d8730f1SJyri Sarha type: object 67*2d8730f1SJyri Sarha description: 68*2d8730f1SJyri Sarha Ports as described in Documentation/devictree/bindings/graph.txt 69*2d8730f1SJyri Sarha properties: 70*2d8730f1SJyri Sarha "#address-cells": 71*2d8730f1SJyri Sarha const: 1 72*2d8730f1SJyri Sarha 73*2d8730f1SJyri Sarha "#size-cells": 74*2d8730f1SJyri Sarha const: 0 75*2d8730f1SJyri Sarha 76*2d8730f1SJyri Sarha port@0: 77*2d8730f1SJyri Sarha type: object 78*2d8730f1SJyri Sarha description: 79*2d8730f1SJyri Sarha The DSS OLDI output port node form video port 1 80*2d8730f1SJyri Sarha 81*2d8730f1SJyri Sarha port@1: 82*2d8730f1SJyri Sarha type: object 83*2d8730f1SJyri Sarha description: 84*2d8730f1SJyri Sarha The DSS DPI output port node from video port 2 85*2d8730f1SJyri Sarha 86*2d8730f1SJyri Sarha required: 87*2d8730f1SJyri Sarha - "#address-cells" 88*2d8730f1SJyri Sarha - "#size-cells" 89*2d8730f1SJyri Sarha 90*2d8730f1SJyri Sarha ti,am65x-oldi-io-ctrl: 91*2d8730f1SJyri Sarha allOf: 92*2d8730f1SJyri Sarha - $ref: "/schemas/types.yaml#/definitions/phandle-array" 93*2d8730f1SJyri Sarha - maxItems: 1 94*2d8730f1SJyri Sarha description: 95*2d8730f1SJyri Sarha phandle to syscon device node mapping OLDI IO_CTRL registers. 96*2d8730f1SJyri Sarha The mapped range should point to OLDI_DAT0_IO_CTRL, map it and 97*2d8730f1SJyri Sarha following OLDI_DAT1_IO_CTRL, OLDI_DAT2_IO_CTRL, OLDI_DAT3_IO_CTRL, 98*2d8730f1SJyri Sarha and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI 99*2d8730f1SJyri Sarha interface to work. 100*2d8730f1SJyri Sarha 101*2d8730f1SJyri Sarha max-memory-bandwidth: 102*2d8730f1SJyri Sarha $ref: /schemas/types.yaml#/definitions/uint32 103*2d8730f1SJyri Sarha description: 104*2d8730f1SJyri Sarha Input memory (from main memory to dispc) bandwidth limit in 105*2d8730f1SJyri Sarha bytes per second 106*2d8730f1SJyri Sarha 107*2d8730f1SJyri Sarharequired: 108*2d8730f1SJyri Sarha - compatible 109*2d8730f1SJyri Sarha - reg 110*2d8730f1SJyri Sarha - reg-names 111*2d8730f1SJyri Sarha - clocks 112*2d8730f1SJyri Sarha - clock-names 113*2d8730f1SJyri Sarha - interrupts 114*2d8730f1SJyri Sarha - ports 115*2d8730f1SJyri Sarha 116*2d8730f1SJyri SarhaadditionalProperties: false 117*2d8730f1SJyri Sarha 118*2d8730f1SJyri Sarhaexamples: 119*2d8730f1SJyri Sarha - | 120*2d8730f1SJyri Sarha #include <dt-bindings/interrupt-controller/arm-gic.h> 121*2d8730f1SJyri Sarha #include <dt-bindings/interrupt-controller/irq.h> 122*2d8730f1SJyri Sarha #include <dt-bindings/soc/ti,sci_pm_domain.h> 123*2d8730f1SJyri Sarha 124*2d8730f1SJyri Sarha dss: dss@04a00000 { 125*2d8730f1SJyri Sarha compatible = "ti,am65x-dss"; 126*2d8730f1SJyri Sarha reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ 127*2d8730f1SJyri Sarha <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ 128*2d8730f1SJyri Sarha <0x0 0x04a06000 0x0 0x1000>, /* vid */ 129*2d8730f1SJyri Sarha <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ 130*2d8730f1SJyri Sarha <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ 131*2d8730f1SJyri Sarha <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ 132*2d8730f1SJyri Sarha <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ 133*2d8730f1SJyri Sarha reg-names = "common", "vidl1", "vid", 134*2d8730f1SJyri Sarha "ovr1", "ovr2", "vp1", "vp2"; 135*2d8730f1SJyri Sarha ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; 136*2d8730f1SJyri Sarha power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 137*2d8730f1SJyri Sarha clocks = <&k3_clks 67 1>, 138*2d8730f1SJyri Sarha <&k3_clks 216 1>, 139*2d8730f1SJyri Sarha <&k3_clks 67 2>; 140*2d8730f1SJyri Sarha clock-names = "fck", "vp1", "vp2"; 141*2d8730f1SJyri Sarha interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>; 142*2d8730f1SJyri Sarha ports { 143*2d8730f1SJyri Sarha #address-cells = <1>; 144*2d8730f1SJyri Sarha #size-cells = <0>; 145*2d8730f1SJyri Sarha port@0 { 146*2d8730f1SJyri Sarha reg = <0>; 147*2d8730f1SJyri Sarha oldi_out0: endpoint { 148*2d8730f1SJyri Sarha remote-endpoint = <&lcd_in0>; 149*2d8730f1SJyri Sarha }; 150*2d8730f1SJyri Sarha }; 151*2d8730f1SJyri Sarha }; 152*2d8730f1SJyri Sarha }; 153