xref: /openbmc/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml (revision e96150a6dc146779fc67a9a016339d861b5ec05a) 
1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm8250-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8250 Display MDSS
8
9maintainers:
10  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11
12description:
13  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15  bindings of MDSS are mentioned for SM8250 target.
16
17$ref: /schemas/display/msm/mdss-common.yaml#
18
19properties:
20  compatible:
21    items:
22      - const: qcom,sm8250-mdss
23
24  clocks:
25    items:
26      - description: Display AHB clock from gcc
27      - description: Display hf axi clock
28      - description: Display sf axi clock
29      - description: Display core clock
30
31  clock-names:
32    items:
33      - const: iface
34      - const: bus
35      - const: nrt_bus
36      - const: core
37
38  iommus:
39    maxItems: 1
40
41  interconnects:
42    maxItems: 2
43
44  interconnect-names:
45    maxItems: 2
46
47patternProperties:
48  "^display-controller@[0-9a-f]+$":
49    type: object
50    properties:
51      compatible:
52        const: qcom,sm8250-dpu
53
54  "^dsi@[0-9a-f]+$":
55    type: object
56    properties:
57      compatible:
58        const: qcom,mdss-dsi-ctrl
59
60  "^phy@[0-9a-f]+$":
61    type: object
62    properties:
63      compatible:
64        const: qcom,dsi-phy-7nm
65
66required:
67  - compatible
68
69unevaluatedProperties: false
70
71examples:
72  - |
73    #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
74    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
75    #include <dt-bindings/clock/qcom,rpmh.h>
76    #include <dt-bindings/interrupt-controller/arm-gic.h>
77    #include <dt-bindings/interconnect/qcom,sm8250.h>
78    #include <dt-bindings/power/qcom-rpmpd.h>
79
80    display-subsystem@ae00000 {
81        compatible = "qcom,sm8250-mdss";
82        reg = <0x0ae00000 0x1000>;
83        reg-names = "mdss";
84
85        interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
86                        <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
87        interconnect-names = "mdp0-mem", "mdp1-mem";
88
89        power-domains = <&dispcc MDSS_GDSC>;
90
91        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
92                 <&gcc GCC_DISP_HF_AXI_CLK>,
93                 <&gcc GCC_DISP_SF_AXI_CLK>,
94                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
95        clock-names = "iface", "bus", "nrt_bus", "core";
96
97        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
98        interrupt-controller;
99        #interrupt-cells = <1>;
100
101        iommus = <&apps_smmu 0x820 0x402>;
102
103        #address-cells = <1>;
104        #size-cells = <1>;
105        ranges;
106
107        display-controller@ae01000 {
108            compatible = "qcom,sm8250-dpu";
109            reg = <0x0ae01000 0x8f000>,
110                  <0x0aeb0000 0x2008>;
111            reg-names = "mdp", "vbif";
112
113            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
114                     <&gcc GCC_DISP_HF_AXI_CLK>,
115                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
116                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
117            clock-names = "iface", "bus", "core", "vsync";
118
119            assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
120            assigned-clock-rates = <19200000>;
121
122            operating-points-v2 = <&mdp_opp_table>;
123            power-domains = <&rpmhpd SM8250_MMCX>;
124
125            interrupt-parent = <&mdss>;
126            interrupts = <0>;
127
128            ports {
129                #address-cells = <1>;
130                #size-cells = <0>;
131
132                port@0 {
133                    reg = <0>;
134                    dpu_intf1_out: endpoint {
135                        remote-endpoint = <&dsi0_in>;
136                    };
137                };
138
139                port@1 {
140                    reg = <1>;
141                    dpu_intf2_out: endpoint {
142                        remote-endpoint = <&dsi1_in>;
143                    };
144                };
145            };
146
147            mdp_opp_table: opp-table {
148                compatible = "operating-points-v2";
149
150                opp-200000000 {
151                    opp-hz = /bits/ 64 <200000000>;
152                    required-opps = <&rpmhpd_opp_low_svs>;
153                };
154
155                opp-300000000 {
156                    opp-hz = /bits/ 64 <300000000>;
157                    required-opps = <&rpmhpd_opp_svs>;
158                };
159
160                opp-345000000 {
161                    opp-hz = /bits/ 64 <345000000>;
162                    required-opps = <&rpmhpd_opp_svs_l1>;
163                };
164
165                opp-460000000 {
166                    opp-hz = /bits/ 64 <460000000>;
167                    required-opps = <&rpmhpd_opp_nom>;
168                };
169            };
170        };
171
172        dsi@ae94000 {
173            compatible = "qcom,mdss-dsi-ctrl";
174            reg = <0x0ae94000 0x400>;
175            reg-names = "dsi_ctrl";
176
177            interrupt-parent = <&mdss>;
178            interrupts = <4>;
179
180            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
181                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
182                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
183                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
184                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
185                     <&gcc GCC_DISP_HF_AXI_CLK>;
186            clock-names = "byte",
187                          "byte_intf",
188                          "pixel",
189                          "core",
190                          "iface",
191                          "bus";
192
193            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
194                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
195            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
196
197            operating-points-v2 = <&dsi_opp_table>;
198            power-domains = <&rpmhpd SM8250_MMCX>;
199
200            phys = <&dsi0_phy>;
201            phy-names = "dsi";
202
203            #address-cells = <1>;
204            #size-cells = <0>;
205
206            ports {
207                #address-cells = <1>;
208                #size-cells = <0>;
209
210                port@0 {
211                    reg = <0>;
212                    dsi0_in: endpoint {
213                        remote-endpoint = <&dpu_intf1_out>;
214                    };
215                };
216
217                port@1 {
218                    reg = <1>;
219                    dsi0_out: endpoint {
220                    };
221                };
222            };
223
224            dsi_opp_table: opp-table {
225                compatible = "operating-points-v2";
226
227                opp-187500000 {
228                    opp-hz = /bits/ 64 <187500000>;
229                    required-opps = <&rpmhpd_opp_low_svs>;
230                };
231
232                opp-300000000 {
233                    opp-hz = /bits/ 64 <300000000>;
234                    required-opps = <&rpmhpd_opp_svs>;
235                };
236
237                opp-358000000 {
238                    opp-hz = /bits/ 64 <358000000>;
239                    required-opps = <&rpmhpd_opp_svs_l1>;
240                };
241            };
242        };
243
244        dsi0_phy: phy@ae94400 {
245            compatible = "qcom,dsi-phy-7nm";
246            reg = <0x0ae94400 0x200>,
247                  <0x0ae94600 0x280>,
248                  <0x0ae94900 0x260>;
249            reg-names = "dsi_phy",
250                        "dsi_phy_lane",
251                        "dsi_pll";
252
253            #clock-cells = <1>;
254            #phy-cells = <0>;
255
256            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
257                     <&rpmhcc RPMH_CXO_CLK>;
258            clock-names = "iface", "ref";
259            vdds-supply = <&vreg_dsi_phy>;
260        };
261
262        dsi@ae96000 {
263            compatible = "qcom,mdss-dsi-ctrl";
264            reg = <0x0ae96000 0x400>;
265            reg-names = "dsi_ctrl";
266
267            interrupt-parent = <&mdss>;
268            interrupts = <5>;
269
270            clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
271                     <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
272                     <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
273                     <&dispcc DISP_CC_MDSS_ESC1_CLK>,
274                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
275                     <&gcc GCC_DISP_HF_AXI_CLK>;
276            clock-names = "byte",
277                          "byte_intf",
278                          "pixel",
279                          "core",
280                          "iface",
281                          "bus";
282
283            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
284                              <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
285            assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
286
287            operating-points-v2 = <&dsi_opp_table>;
288            power-domains = <&rpmhpd SM8250_MMCX>;
289
290            phys = <&dsi1_phy>;
291            phy-names = "dsi";
292
293            #address-cells = <1>;
294            #size-cells = <0>;
295
296            ports {
297                #address-cells = <1>;
298                #size-cells = <0>;
299
300                port@0 {
301                    reg = <0>;
302                    dsi1_in: endpoint {
303                        remote-endpoint = <&dpu_intf2_out>;
304                    };
305                };
306
307                port@1 {
308                    reg = <1>;
309                    dsi1_out: endpoint {
310                    };
311                };
312            };
313        };
314
315        dsi1_phy: phy@ae96400 {
316            compatible = "qcom,dsi-phy-7nm";
317            reg = <0x0ae96400 0x200>,
318                  <0x0ae96600 0x280>,
319                  <0x0ae96900 0x260>;
320            reg-names = "dsi_phy",
321                        "dsi_phy_lane",
322                        "dsi_pll";
323
324            #clock-cells = <1>;
325            #phy-cells = <0>;
326
327            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
328                     <&rpmhcc RPMH_CXO_CLK>;
329            clock-names = "iface", "ref";
330            vdds-supply = <&vreg_dsi_phy>;
331        };
332    };
333...
334