xref: /openbmc/linux/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml (revision e96150a6dc146779fc67a9a016339d861b5ec05a) 
1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SC7280 Display MDSS
8
9maintainers:
10  - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12description:
13  Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
14  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15  bindings of MDSS are mentioned for SC7280.
16
17$ref: /schemas/display/msm/mdss-common.yaml#
18
19properties:
20  compatible:
21    const: qcom,sc7280-mdss
22
23  clocks:
24    items:
25      - description: Display AHB clock from gcc
26      - description: Display AHB clock from dispcc
27      - description: Display core clock
28
29  clock-names:
30    items:
31      - const: iface
32      - const: ahb
33      - const: core
34
35  iommus:
36    maxItems: 1
37
38  interconnects:
39    maxItems: 1
40
41  interconnect-names:
42    maxItems: 1
43
44patternProperties:
45  "^display-controller@[0-9a-f]+$":
46    type: object
47    properties:
48      compatible:
49        const: qcom,sc7280-dpu
50
51  "^displayport-controller@[0-9a-f]+$":
52    type: object
53    properties:
54      compatible:
55        const: qcom,sc7280-dp
56
57  "^dsi@[0-9a-f]+$":
58    type: object
59    properties:
60      compatible:
61        const: qcom,mdss-dsi-ctrl
62
63  "^edp@[0-9a-f]+$":
64    type: object
65    properties:
66      compatible:
67        const: qcom,sc7280-edp
68
69  "^phy@[0-9a-f]+$":
70    type: object
71    properties:
72      compatible:
73        enum:
74          - qcom,sc7280-dsi-phy-7nm
75          - qcom,sc7280-edp-phy
76
77required:
78  - compatible
79
80unevaluatedProperties: false
81
82examples:
83  - |
84    #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
85    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
86    #include <dt-bindings/clock/qcom,rpmh.h>
87    #include <dt-bindings/interrupt-controller/arm-gic.h>
88    #include <dt-bindings/interconnect/qcom,sc7280.h>
89    #include <dt-bindings/power/qcom-rpmpd.h>
90
91    display-subsystem@ae00000 {
92        #address-cells = <1>;
93        #size-cells = <1>;
94        compatible = "qcom,sc7280-mdss";
95        reg = <0xae00000 0x1000>;
96        reg-names = "mdss";
97        power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
98        clocks = <&gcc GCC_DISP_AHB_CLK>,
99                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
100                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
101        clock-names = "iface",
102                      "ahb",
103                      "core";
104
105        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
106        interrupt-controller;
107        #interrupt-cells = <1>;
108
109        interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
110        interconnect-names = "mdp0-mem";
111
112        iommus = <&apps_smmu 0x900 0x402>;
113        ranges;
114
115        display-controller@ae01000 {
116            compatible = "qcom,sc7280-dpu";
117            reg = <0x0ae01000 0x8f000>,
118                  <0x0aeb0000 0x2008>;
119
120            reg-names = "mdp", "vbif";
121
122            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
123                     <&gcc GCC_DISP_SF_AXI_CLK>,
124                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
125                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
126                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
127                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
128            clock-names = "bus",
129                          "nrt_bus",
130                          "iface",
131                          "lut",
132                          "core",
133                          "vsync";
134
135            interrupt-parent = <&mdss>;
136            interrupts = <0>;
137            power-domains = <&rpmhpd SC7280_CX>;
138            operating-points-v2 = <&mdp_opp_table>;
139
140            ports {
141                #address-cells = <1>;
142                #size-cells = <0>;
143
144                port@0 {
145                    reg = <0>;
146                    dpu_intf1_out: endpoint {
147                        remote-endpoint = <&dsi0_in>;
148                    };
149                };
150
151                port@1 {
152                    reg = <1>;
153                    dpu_intf5_out: endpoint {
154                        remote-endpoint = <&edp_in>;
155                    };
156                };
157
158                port@2 {
159                    reg = <2>;
160                    dpu_intf0_out: endpoint {
161                        remote-endpoint = <&dp_in>;
162                    };
163                };
164            };
165        };
166
167        dsi@ae94000 {
168            compatible = "qcom,mdss-dsi-ctrl";
169            reg = <0x0ae94000 0x400>;
170            reg-names = "dsi_ctrl";
171
172            interrupt-parent = <&mdss>;
173            interrupts = <4>;
174
175            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
176                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
177                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
178                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
179                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
180                     <&gcc GCC_DISP_HF_AXI_CLK>;
181            clock-names = "byte",
182                          "byte_intf",
183                          "pixel",
184                          "core",
185                          "iface",
186                          "bus";
187
188            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
189                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
190            assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
191
192            operating-points-v2 = <&dsi_opp_table>;
193            power-domains = <&rpmhpd SC7280_CX>;
194
195            phys = <&mdss_dsi_phy>;
196            phy-names = "dsi";
197
198            #address-cells = <1>;
199            #size-cells = <0>;
200
201            ports {
202                #address-cells = <1>;
203                #size-cells = <0>;
204
205                port@0 {
206                    reg = <0>;
207                    dsi0_in: endpoint {
208                        remote-endpoint = <&dpu_intf1_out>;
209                    };
210                };
211
212                port@1 {
213                    reg = <1>;
214                    dsi0_out: endpoint {
215                    };
216                };
217            };
218
219            dsi_opp_table: opp-table {
220                compatible = "operating-points-v2";
221
222                opp-187500000 {
223                    opp-hz = /bits/ 64 <187500000>;
224                    required-opps = <&rpmhpd_opp_low_svs>;
225                };
226
227                opp-300000000 {
228                    opp-hz = /bits/ 64 <300000000>;
229                    required-opps = <&rpmhpd_opp_svs>;
230                };
231
232                opp-358000000 {
233                    opp-hz = /bits/ 64 <358000000>;
234                    required-opps = <&rpmhpd_opp_svs_l1>;
235                };
236            };
237        };
238
239        mdss_dsi_phy: phy@ae94400 {
240            compatible = "qcom,sc7280-dsi-phy-7nm";
241            reg = <0x0ae94400 0x200>,
242                  <0x0ae94600 0x280>,
243                  <0x0ae94900 0x280>;
244            reg-names = "dsi_phy",
245                        "dsi_phy_lane",
246                        "dsi_pll";
247
248            #clock-cells = <1>;
249            #phy-cells = <0>;
250
251            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
252                     <&rpmhcc RPMH_CXO_CLK>;
253            clock-names = "iface", "ref";
254
255            vdds-supply = <&vreg_dsi_supply>;
256        };
257
258        edp@aea0000 {
259            compatible = "qcom,sc7280-edp";
260            pinctrl-names = "default";
261            pinctrl-0 = <&edp_hot_plug_det>;
262
263            reg = <0xaea0000 0x200>,
264                  <0xaea0200 0x200>,
265                  <0xaea0400 0xc00>,
266                  <0xaea1000 0x400>;
267
268            interrupt-parent = <&mdss>;
269            interrupts = <14>;
270
271            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
272                     <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
273                     <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
274                     <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
275                     <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
276            clock-names = "core_iface",
277                          "core_aux",
278                          "ctrl_link",
279                          "ctrl_link_iface",
280                          "stream_pixel";
281            assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
282                              <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
283            assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
284
285            phys = <&mdss_edp_phy>;
286            phy-names = "dp";
287
288            operating-points-v2 = <&edp_opp_table>;
289            power-domains = <&rpmhpd SC7280_CX>;
290
291            ports {
292                #address-cells = <1>;
293                #size-cells = <0>;
294
295                port@0 {
296                    reg = <0>;
297                    edp_in: endpoint {
298                        remote-endpoint = <&dpu_intf5_out>;
299                    };
300                };
301
302                port@1 {
303                    reg = <1>;
304                    mdss_edp_out: endpoint { };
305                };
306            };
307
308            edp_opp_table: opp-table {
309                compatible = "operating-points-v2";
310
311                opp-160000000 {
312                    opp-hz = /bits/ 64 <160000000>;
313                    required-opps = <&rpmhpd_opp_low_svs>;
314                };
315
316                opp-270000000 {
317                    opp-hz = /bits/ 64 <270000000>;
318                    required-opps = <&rpmhpd_opp_svs>;
319                };
320
321                opp-540000000 {
322                    opp-hz = /bits/ 64 <540000000>;
323                    required-opps = <&rpmhpd_opp_nom>;
324                };
325
326                opp-810000000 {
327                    opp-hz = /bits/ 64 <810000000>;
328                    required-opps = <&rpmhpd_opp_nom>;
329                };
330            };
331        };
332
333        mdss_edp_phy: phy@aec2a00 {
334            compatible = "qcom,sc7280-edp-phy";
335
336            reg = <0xaec2a00 0x19c>,
337                  <0xaec2200 0xa0>,
338                  <0xaec2600 0xa0>,
339                  <0xaec2000 0x1c0>;
340
341            clocks = <&rpmhcc RPMH_CXO_CLK>,
342                     <&gcc GCC_EDP_CLKREF_EN>;
343            clock-names = "aux",
344                          "cfg_ahb";
345
346            #clock-cells = <1>;
347            #phy-cells = <0>;
348        };
349
350        displayport-controller@ae90000 {
351            compatible = "qcom,sc7280-dp";
352
353            reg = <0xae90000 0x200>,
354                  <0xae90200 0x200>,
355                  <0xae90400 0xc00>,
356                  <0xae91000 0x400>,
357                  <0xae91400 0x400>;
358
359            interrupt-parent = <&mdss>;
360            interrupts = <12>;
361
362            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
363                     <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
364                     <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
365                     <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
366                     <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
367            clock-names = "core_iface",
368                          "core_aux",
369                          "ctrl_link",
370                          "ctrl_link_iface",
371                          "stream_pixel";
372            assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
373                              <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
374            assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
375            phys = <&dp_phy>;
376            phy-names = "dp";
377
378            operating-points-v2 = <&dp_opp_table>;
379            power-domains = <&rpmhpd SC7280_CX>;
380
381            #sound-dai-cells = <0>;
382
383            ports {
384                #address-cells = <1>;
385                #size-cells = <0>;
386
387                port@0 {
388                    reg = <0>;
389                    dp_in: endpoint {
390                        remote-endpoint = <&dpu_intf0_out>;
391                    };
392                };
393
394                port@1 {
395                    reg = <1>;
396                    dp_out: endpoint { };
397                };
398            };
399
400            dp_opp_table: opp-table {
401                compatible = "operating-points-v2";
402
403                opp-160000000 {
404                    opp-hz = /bits/ 64 <160000000>;
405                    required-opps = <&rpmhpd_opp_low_svs>;
406                };
407
408                opp-270000000 {
409                    opp-hz = /bits/ 64 <270000000>;
410                    required-opps = <&rpmhpd_opp_svs>;
411                };
412
413                opp-540000000 {
414                    opp-hz = /bits/ 64 <540000000>;
415                    required-opps = <&rpmhpd_opp_svs_l1>;
416                };
417
418                opp-810000000 {
419                    opp-hz = /bits/ 64 <810000000>;
420                    required-opps = <&rpmhpd_opp_nom>;
421                };
422            };
423        };
424    };
425...
426