1f5a98bfeSMaxime Ripard# SPDX-License-Identifier: GPL-2.0 2f5a98bfeSMaxime Ripard%YAML 1.2 3f5a98bfeSMaxime Ripard--- 4f5a98bfeSMaxime Ripard$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-frontend.yaml# 5f5a98bfeSMaxime Ripard$schema: http://devicetree.org/meta-schemas/core.yaml# 6f5a98bfeSMaxime Ripard 7*dd3cb467SAndrew Lunntitle: Allwinner A10 Display Engine Frontend 8f5a98bfeSMaxime Ripard 9f5a98bfeSMaxime Ripardmaintainers: 10f5a98bfeSMaxime Ripard - Chen-Yu Tsai <wens@csie.org> 11f5a98bfeSMaxime Ripard - Maxime Ripard <mripard@kernel.org> 12f5a98bfeSMaxime Ripard 13f5a98bfeSMaxime Riparddescription: | 14f5a98bfeSMaxime Ripard The display engine frontend does formats conversion, scaling, 15f5a98bfeSMaxime Ripard deinterlacing and color space conversion. 16f5a98bfeSMaxime Ripard 17f5a98bfeSMaxime Ripardproperties: 18f5a98bfeSMaxime Ripard compatible: 19f5a98bfeSMaxime Ripard enum: 20f5a98bfeSMaxime Ripard - allwinner,sun4i-a10-display-frontend 21f5a98bfeSMaxime Ripard - allwinner,sun5i-a13-display-frontend 22f5a98bfeSMaxime Ripard - allwinner,sun6i-a31-display-frontend 23f5a98bfeSMaxime Ripard - allwinner,sun7i-a20-display-frontend 24f5a98bfeSMaxime Ripard - allwinner,sun8i-a23-display-frontend 25f5a98bfeSMaxime Ripard - allwinner,sun8i-a33-display-frontend 26f5a98bfeSMaxime Ripard - allwinner,sun9i-a80-display-frontend 27f5a98bfeSMaxime Ripard 28f5a98bfeSMaxime Ripard reg: 29f5a98bfeSMaxime Ripard maxItems: 1 30f5a98bfeSMaxime Ripard 31f5a98bfeSMaxime Ripard interrupts: 32f5a98bfeSMaxime Ripard maxItems: 1 33f5a98bfeSMaxime Ripard 34f5a98bfeSMaxime Ripard clocks: 35f5a98bfeSMaxime Ripard items: 36f5a98bfeSMaxime Ripard - description: The frontend interface clock 37f5a98bfeSMaxime Ripard - description: The frontend module clock 38f5a98bfeSMaxime Ripard - description: The frontend DRAM clock 39f5a98bfeSMaxime Ripard 40f5a98bfeSMaxime Ripard clock-names: 41f5a98bfeSMaxime Ripard items: 42f5a98bfeSMaxime Ripard - const: ahb 43f5a98bfeSMaxime Ripard - const: mod 44f5a98bfeSMaxime Ripard - const: ram 45f5a98bfeSMaxime Ripard 46f5a98bfeSMaxime Ripard # FIXME: This should be made required eventually once every SoC will 47f5a98bfeSMaxime Ripard # have the MBUS declared. 48f5a98bfeSMaxime Ripard interconnects: 49f5a98bfeSMaxime Ripard maxItems: 1 50f5a98bfeSMaxime Ripard 51f5a98bfeSMaxime Ripard # FIXME: This should be made required eventually once every SoC will 52f5a98bfeSMaxime Ripard # have the MBUS declared. 53f5a98bfeSMaxime Ripard interconnect-names: 54f5a98bfeSMaxime Ripard const: dma-mem 55f5a98bfeSMaxime Ripard 56f5a98bfeSMaxime Ripard resets: 57f5a98bfeSMaxime Ripard maxItems: 1 58f5a98bfeSMaxime Ripard 59f5a98bfeSMaxime Ripard ports: 60b6755423SRob Herring $ref: /schemas/graph.yaml#/properties/ports 61f5a98bfeSMaxime Ripard 62f5a98bfeSMaxime Ripard properties: 63f5a98bfeSMaxime Ripard port@0: 64b6755423SRob Herring $ref: /schemas/graph.yaml#/properties/port 65f5a98bfeSMaxime Ripard description: | 66f5a98bfeSMaxime Ripard Input endpoints of the controller. 67f5a98bfeSMaxime Ripard 68f5a98bfeSMaxime Ripard port@1: 69b6755423SRob Herring $ref: /schemas/graph.yaml#/properties/port 70f5a98bfeSMaxime Ripard description: | 71f5a98bfeSMaxime Ripard Output endpoints of the controller. 72f5a98bfeSMaxime Ripard 73f5a98bfeSMaxime Ripard required: 74f5a98bfeSMaxime Ripard - port@1 75f5a98bfeSMaxime Ripard 76f5a98bfeSMaxime Ripardrequired: 77f5a98bfeSMaxime Ripard - compatible 78f5a98bfeSMaxime Ripard - reg 79f5a98bfeSMaxime Ripard - interrupts 80f5a98bfeSMaxime Ripard - clocks 81f5a98bfeSMaxime Ripard - clock-names 82f5a98bfeSMaxime Ripard - resets 83f5a98bfeSMaxime Ripard - ports 84f5a98bfeSMaxime Ripard 85f5a98bfeSMaxime RipardadditionalProperties: false 86f5a98bfeSMaxime Ripard 87f5a98bfeSMaxime Ripardexamples: 88f5a98bfeSMaxime Ripard - | 89f5a98bfeSMaxime Ripard #include <dt-bindings/clock/sun4i-a10-ccu.h> 90f5a98bfeSMaxime Ripard #include <dt-bindings/reset/sun4i-a10-ccu.h> 91f5a98bfeSMaxime Ripard 92f5a98bfeSMaxime Ripard fe0: display-frontend@1e00000 { 93f5a98bfeSMaxime Ripard compatible = "allwinner,sun4i-a10-display-frontend"; 94f5a98bfeSMaxime Ripard reg = <0x01e00000 0x20000>; 95f5a98bfeSMaxime Ripard interrupts = <47>; 96f5a98bfeSMaxime Ripard clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, 97f5a98bfeSMaxime Ripard <&ccu CLK_DRAM_DE_FE0>; 98f5a98bfeSMaxime Ripard clock-names = "ahb", "mod", 99f5a98bfeSMaxime Ripard "ram"; 100f5a98bfeSMaxime Ripard resets = <&ccu RST_DE_FE0>; 101f5a98bfeSMaxime Ripard 102f5a98bfeSMaxime Ripard ports { 103f5a98bfeSMaxime Ripard #address-cells = <1>; 104f5a98bfeSMaxime Ripard #size-cells = <0>; 105f5a98bfeSMaxime Ripard 106f5a98bfeSMaxime Ripard fe0_out: port@1 { 107f5a98bfeSMaxime Ripard #address-cells = <1>; 108f5a98bfeSMaxime Ripard #size-cells = <0>; 109f5a98bfeSMaxime Ripard reg = <1>; 110f5a98bfeSMaxime Ripard 111f5a98bfeSMaxime Ripard fe0_out_be0: endpoint@0 { 112f5a98bfeSMaxime Ripard reg = <0>; 113f5a98bfeSMaxime Ripard remote-endpoint = <&be0_in_fe0>; 114f5a98bfeSMaxime Ripard }; 115f5a98bfeSMaxime Ripard 116f5a98bfeSMaxime Ripard fe0_out_be1: endpoint@1 { 117f5a98bfeSMaxime Ripard reg = <1>; 118f5a98bfeSMaxime Ripard remote-endpoint = <&be1_in_fe0>; 119f5a98bfeSMaxime Ripard }; 120f5a98bfeSMaxime Ripard }; 121f5a98bfeSMaxime Ripard }; 122f5a98bfeSMaxime Ripard }; 123f5a98bfeSMaxime Ripard 124f5a98bfeSMaxime Ripard 125f5a98bfeSMaxime Ripard... 126