xref: /openbmc/linux/Documentation/devicetree/bindings/crypto/qcom-qce.yaml (revision c168dc4b513b66e24ff70800203406c41579ace2)
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/crypto/qcom-qce.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm crypto engine driver
8
9maintainers:
10  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
11
12description:
13  This document defines the binding for the QCE crypto
14  controller found on Qualcomm parts.
15
16properties:
17  compatible:
18    const: qcom,crypto-v5.1
19
20  reg:
21    maxItems: 1
22
23  clocks:
24    items:
25      - description: iface clocks register interface.
26      - description: bus clocks data transfer interface.
27      - description: core clocks rest of the crypto block.
28
29  clock-names:
30    items:
31      - const: iface
32      - const: bus
33      - const: core
34
35  iommus:
36    minItems: 1
37    maxItems: 8
38    description:
39      phandle to apps_smmu node with sid mask.
40
41  interconnects:
42    maxItems: 1
43    description:
44      Interconnect path between qce crypto and main memory.
45
46  interconnect-names:
47    const: memory
48
49  dmas:
50    items:
51      - description: DMA specifiers for rx dma channel.
52      - description: DMA specifiers for tx dma channel.
53
54  dma-names:
55    items:
56      - const: rx
57      - const: tx
58
59required:
60  - compatible
61  - reg
62  - clocks
63  - clock-names
64  - dmas
65  - dma-names
66
67additionalProperties: false
68
69examples:
70  - |
71    #include <dt-bindings/clock/qcom,gcc-apq8084.h>
72    crypto-engine@fd45a000 {
73        compatible = "qcom,crypto-v5.1";
74        reg = <0xfd45a000 0x6000>;
75        clocks = <&gcc GCC_CE2_AHB_CLK>,
76                 <&gcc GCC_CE2_AXI_CLK>,
77                 <&gcc GCC_CE2_CLK>;
78        clock-names = "iface", "bus", "core";
79        dmas = <&cryptobam 2>, <&cryptobam 3>;
80        dma-names = "rx", "tx";
81        iommus = <&apps_smmu 0x584 0x0011>,
82                 <&apps_smmu 0x586 0x0011>,
83                 <&apps_smmu 0x594 0x0011>,
84                 <&apps_smmu 0x596 0x0011>;
85    };
86