1*206dc4fcSRob RiceThe Broadcom Secure Processing Unit (SPU) hardware supports symmetric 2*206dc4fcSRob Ricecryptographic offload for Broadcom SoCs. A SoC may have multiple SPU hardware 3*206dc4fcSRob Riceblocks. 4*206dc4fcSRob Rice 5*206dc4fcSRob RiceRequired properties: 6*206dc4fcSRob Rice- compatible: Should be one of the following: 7*206dc4fcSRob Rice brcm,spum-crypto - for devices with SPU-M hardware 8*206dc4fcSRob Rice brcm,spu2-crypto - for devices with SPU2 hardware 9*206dc4fcSRob Rice brcm,spu2-v2-crypto - for devices with enhanced SPU2 hardware features like SHA3 10*206dc4fcSRob Rice and Rabin Fingerprint support 11*206dc4fcSRob Rice brcm,spum-nsp-crypto - for the Northstar Plus variant of the SPU-M hardware 12*206dc4fcSRob Rice 13*206dc4fcSRob Rice- reg: Should contain SPU registers location and length. 14*206dc4fcSRob Rice- mboxes: The mailbox channel to be used to communicate with the SPU. 15*206dc4fcSRob Rice Mailbox channels correspond to DMA rings on the device. 16*206dc4fcSRob Rice 17*206dc4fcSRob RiceExample: 18*206dc4fcSRob Rice crypto@612d0000 { 19*206dc4fcSRob Rice compatible = "brcm,spum-crypto"; 20*206dc4fcSRob Rice reg = <0 0x612d0000 0 0x900>; 21*206dc4fcSRob Rice mboxes = <&pdc0 0>; 22*206dc4fcSRob Rice }; 23