1eba8ba8aSChunyan Zhang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2eba8ba8aSChunyan Zhang# Copyright 2019 Unisoc Inc. 3eba8ba8aSChunyan Zhang%YAML 1.2 4eba8ba8aSChunyan Zhang--- 532671977SRob Herring$id: http://devicetree.org/schemas/clock/sprd,sc9863a-clk.yaml# 632671977SRob Herring$schema: http://devicetree.org/meta-schemas/core.yaml# 7eba8ba8aSChunyan Zhang 8dd3cb467SAndrew Lunntitle: SC9863A Clock Control Unit 9eba8ba8aSChunyan Zhang 10eba8ba8aSChunyan Zhangmaintainers: 11eba8ba8aSChunyan Zhang - Orson Zhai <orsonzhai@gmail.com> 12eba8ba8aSChunyan Zhang - Baolin Wang <baolin.wang7@gmail.com> 13eba8ba8aSChunyan Zhang - Chunyan Zhang <zhang.lyra@gmail.com> 14eba8ba8aSChunyan Zhang 15eba8ba8aSChunyan Zhangproperties: 16eba8ba8aSChunyan Zhang "#clock-cells": 17eba8ba8aSChunyan Zhang const: 1 18eba8ba8aSChunyan Zhang 19eba8ba8aSChunyan Zhang compatible: 20eba8ba8aSChunyan Zhang enum: 21eba8ba8aSChunyan Zhang - sprd,sc9863a-ap-clk 22eba8ba8aSChunyan Zhang - sprd,sc9863a-aon-clk 23eba8ba8aSChunyan Zhang - sprd,sc9863a-apahb-gate 24eba8ba8aSChunyan Zhang - sprd,sc9863a-pmu-gate 25eba8ba8aSChunyan Zhang - sprd,sc9863a-aonapb-gate 26eba8ba8aSChunyan Zhang - sprd,sc9863a-pll 27eba8ba8aSChunyan Zhang - sprd,sc9863a-mpll 28eba8ba8aSChunyan Zhang - sprd,sc9863a-rpll 29eba8ba8aSChunyan Zhang - sprd,sc9863a-dpll 30eba8ba8aSChunyan Zhang - sprd,sc9863a-mm-gate 3182a4d4a7SChunyan Zhang - sprd,sc9863a-mm-clk 32eba8ba8aSChunyan Zhang - sprd,sc9863a-apapb-gate 33eba8ba8aSChunyan Zhang 34eba8ba8aSChunyan Zhang clocks: 35eba8ba8aSChunyan Zhang minItems: 1 36eba8ba8aSChunyan Zhang maxItems: 4 37eba8ba8aSChunyan Zhang description: | 38eba8ba8aSChunyan Zhang The input parent clock(s) phandle for this clock, only list fixed 39eba8ba8aSChunyan Zhang clocks which are declared in devicetree. 40eba8ba8aSChunyan Zhang 41eba8ba8aSChunyan Zhang clock-names: 42eba8ba8aSChunyan Zhang minItems: 1 43eba8ba8aSChunyan Zhang items: 44eba8ba8aSChunyan Zhang - const: ext-26m 45eba8ba8aSChunyan Zhang - const: ext-32k 46eba8ba8aSChunyan Zhang - const: ext-4m 47eba8ba8aSChunyan Zhang - const: rco-100m 48eba8ba8aSChunyan Zhang 49eba8ba8aSChunyan Zhang reg: 50eba8ba8aSChunyan Zhang maxItems: 1 51eba8ba8aSChunyan Zhang 52eba8ba8aSChunyan Zhangrequired: 53eba8ba8aSChunyan Zhang - compatible 54eba8ba8aSChunyan Zhang - '#clock-cells' 55eba8ba8aSChunyan Zhang 56eba8ba8aSChunyan Zhangif: 57eba8ba8aSChunyan Zhang properties: 58eba8ba8aSChunyan Zhang compatible: 59eba8ba8aSChunyan Zhang enum: 60eba8ba8aSChunyan Zhang - sprd,sc9863a-ap-clk 61eba8ba8aSChunyan Zhang - sprd,sc9863a-aon-clk 62eba8ba8aSChunyan Zhangthen: 63eba8ba8aSChunyan Zhang required: 64eba8ba8aSChunyan Zhang - reg 65eba8ba8aSChunyan Zhang 66eba8ba8aSChunyan Zhangelse: 67eba8ba8aSChunyan Zhang description: | 68eba8ba8aSChunyan Zhang Other SC9863a clock nodes should be the child of a syscon node in 69*47aab533SBjorn Helgaas which compatible string should be: 70eba8ba8aSChunyan Zhang "sprd,sc9863a-glbregs", "syscon", "simple-mfd" 71eba8ba8aSChunyan Zhang 72eba8ba8aSChunyan Zhang The 'reg' property for the clock node is also required if there is a sub 73eba8ba8aSChunyan Zhang range of registers for the clocks. 74eba8ba8aSChunyan Zhang 755be478f9SRob HerringadditionalProperties: false 765be478f9SRob Herring 77eba8ba8aSChunyan Zhangexamples: 78eba8ba8aSChunyan Zhang - | 79eba8ba8aSChunyan Zhang ap_clk: clock-controller@21500000 { 80eba8ba8aSChunyan Zhang compatible = "sprd,sc9863a-ap-clk"; 81fba56184SRob Herring reg = <0x21500000 0x1000>; 82eba8ba8aSChunyan Zhang clocks = <&ext_26m>, <&ext_32k>; 83eba8ba8aSChunyan Zhang clock-names = "ext-26m", "ext-32k"; 84eba8ba8aSChunyan Zhang #clock-cells = <1>; 85eba8ba8aSChunyan Zhang }; 86eba8ba8aSChunyan Zhang 87eba8ba8aSChunyan Zhang - | 88fba56184SRob Herring syscon@20e00000 { 89eba8ba8aSChunyan Zhang compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd"; 90fba56184SRob Herring reg = <0x20e00000 0x4000>; 91eba8ba8aSChunyan Zhang #address-cells = <1>; 92eba8ba8aSChunyan Zhang #size-cells = <1>; 93fba56184SRob Herring ranges = <0 0x20e00000 0x4000>; 94eba8ba8aSChunyan Zhang 95eba8ba8aSChunyan Zhang apahb_gate: apahb-gate@0 { 96eba8ba8aSChunyan Zhang compatible = "sprd,sc9863a-apahb-gate"; 97eba8ba8aSChunyan Zhang reg = <0x0 0x1020>; 98eba8ba8aSChunyan Zhang #clock-cells = <1>; 99eba8ba8aSChunyan Zhang }; 100eba8ba8aSChunyan Zhang }; 101eba8ba8aSChunyan Zhang 102eba8ba8aSChunyan Zhang... 103