1b51af0baSElaine Zhang* Rockchip RK3328 Clock and Reset Unit 2b51af0baSElaine Zhang 3b51af0baSElaine ZhangThe RK3328 clock controller generates and supplies clock to various 4b51af0baSElaine Zhangcontrollers within the SoC and also implements a reset controller for SoC 5b51af0baSElaine Zhangperipherals. 6b51af0baSElaine Zhang 7b51af0baSElaine ZhangRequired Properties: 8b51af0baSElaine Zhang 9b51af0baSElaine Zhang- compatible: should be "rockchip,rk3328-cru" 10b51af0baSElaine Zhang- reg: physical base address of the controller and length of memory mapped 11b51af0baSElaine Zhang region. 12b51af0baSElaine Zhang- #clock-cells: should be 1. 13b51af0baSElaine Zhang- #reset-cells: should be 1. 14b51af0baSElaine Zhang 15b51af0baSElaine ZhangOptional Properties: 16b51af0baSElaine Zhang 17b51af0baSElaine Zhang- rockchip,grf: phandle to the syscon managing the "general register files" 18b51af0baSElaine Zhang If missing pll rates are not changeable, due to the missing pll lock status. 19b51af0baSElaine Zhang 20b51af0baSElaine ZhangEach clock is assigned an identifier and client nodes can use this identifier 21b51af0baSElaine Zhangto specify the clock which they consume. All available clocks are defined as 22b51af0baSElaine Zhangpreprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be 23b51af0baSElaine Zhangused in device tree sources. Similar macros exist for the reset sources in 24b51af0baSElaine Zhangthese files. 25b51af0baSElaine Zhang 26b51af0baSElaine ZhangExternal clocks: 27b51af0baSElaine Zhang 28b51af0baSElaine ZhangThere are several clocks that are generated outside the SoC. It is expected 29b51af0baSElaine Zhangthat they are defined using standard clock bindings with following 30b51af0baSElaine Zhangclock-output-names: 31b51af0baSElaine Zhang - "xin24m" - crystal input - required, 32b51af0baSElaine Zhang - "clkin_i2s" - external I2S clock - optional, 33b51af0baSElaine Zhang - "gmac_clkin" - external GMAC clock - optional 34b51af0baSElaine Zhang - "phy_50m_out" - output clock of the pll in the mac phy 35*dd5bdb79SHeiko Stuebner - "hdmi_phy" - output clock of the hdmi phy pll - optional 36b51af0baSElaine Zhang 37b51af0baSElaine ZhangExample: Clock controller node: 38b51af0baSElaine Zhang 39b51af0baSElaine Zhang cru: clock-controller@ff440000 { 40b51af0baSElaine Zhang compatible = "rockchip,rk3328-cru"; 41b51af0baSElaine Zhang reg = <0x0 0xff440000 0x0 0x1000>; 42b51af0baSElaine Zhang rockchip,grf = <&grf>; 43b51af0baSElaine Zhang 44b51af0baSElaine Zhang #clock-cells = <1>; 45b51af0baSElaine Zhang #reset-cells = <1>; 46b51af0baSElaine Zhang }; 47b51af0baSElaine Zhang 48b51af0baSElaine ZhangExample: UART controller node that consumes the clock generated by the clock 49b51af0baSElaine Zhang controller: 50b51af0baSElaine Zhang 51b51af0baSElaine Zhang uart0: serial@ff120000 { 52b51af0baSElaine Zhang compatible = "snps,dw-apb-uart"; 53b51af0baSElaine Zhang reg = <0xff120000 0x100>; 54b51af0baSElaine Zhang interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 55b51af0baSElaine Zhang reg-shift = <2>; 56b51af0baSElaine Zhang reg-io-width = <4>; 57b51af0baSElaine Zhang clocks = <&cru SCLK_UART0>; 58b51af0baSElaine Zhang }; 59