1*4f83b523SDaniel Palmer# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4f83b523SDaniel Palmer%YAML 1.2 3*4f83b523SDaniel Palmer--- 4*4f83b523SDaniel Palmer$id: http://devicetree.org/schemas/clock/mstar,msc313-mpll.yaml# 5*4f83b523SDaniel Palmer$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4f83b523SDaniel Palmer 7*4f83b523SDaniel Palmertitle: MStar/Sigmastar MSC313 MPLL 8*4f83b523SDaniel Palmer 9*4f83b523SDaniel Palmermaintainers: 10*4f83b523SDaniel Palmer - Daniel Palmer <daniel@thingy.jp> 11*4f83b523SDaniel Palmer 12*4f83b523SDaniel Palmerdescription: | 13*4f83b523SDaniel Palmer The MStar/SigmaStar MSC313 and later ARMv7 chips have an MPLL block that 14*4f83b523SDaniel Palmer takes the external xtal input and multiplies it to create a high 15*4f83b523SDaniel Palmer frequency clock and divides that down into a number of clocks that 16*4f83b523SDaniel Palmer peripherals use. 17*4f83b523SDaniel Palmer 18*4f83b523SDaniel Palmerproperties: 19*4f83b523SDaniel Palmer compatible: 20*4f83b523SDaniel Palmer const: mstar,msc313-mpll 21*4f83b523SDaniel Palmer 22*4f83b523SDaniel Palmer "#clock-cells": 23*4f83b523SDaniel Palmer const: 1 24*4f83b523SDaniel Palmer 25*4f83b523SDaniel Palmer clocks: 26*4f83b523SDaniel Palmer maxItems: 1 27*4f83b523SDaniel Palmer 28*4f83b523SDaniel Palmer reg: 29*4f83b523SDaniel Palmer maxItems: 1 30*4f83b523SDaniel Palmer 31*4f83b523SDaniel Palmerrequired: 32*4f83b523SDaniel Palmer - compatible 33*4f83b523SDaniel Palmer - "#clock-cells" 34*4f83b523SDaniel Palmer - clocks 35*4f83b523SDaniel Palmer - reg 36*4f83b523SDaniel Palmer 37*4f83b523SDaniel PalmeradditionalProperties: false 38*4f83b523SDaniel Palmer 39*4f83b523SDaniel Palmerexamples: 40*4f83b523SDaniel Palmer - | 41*4f83b523SDaniel Palmer mpll@206000 { 42*4f83b523SDaniel Palmer compatible = "mstar,msc313-mpll"; 43*4f83b523SDaniel Palmer reg = <0x206000 0x200>; 44*4f83b523SDaniel Palmer #clock-cells = <1>; 45*4f83b523SDaniel Palmer clocks = <&xtal>; 46*4f83b523SDaniel Palmer }; 47