1*2bc61da9SChao Xie* Marvell PXA910 Clock Controller 2*2bc61da9SChao Xie 3*2bc61da9SChao XieThe PXA910 clock subsystem generates and supplies clock to various 4*2bc61da9SChao Xiecontrollers within the PXA910 SoC. 5*2bc61da9SChao Xie 6*2bc61da9SChao XieRequired Properties: 7*2bc61da9SChao Xie 8*2bc61da9SChao Xie- compatible: should be one of the following. 9*2bc61da9SChao Xie - "marvell,pxa910-clock" - controller compatible with PXA910 SoC. 10*2bc61da9SChao Xie 11*2bc61da9SChao Xie- reg: physical base address of the clock subsystem and length of memory mapped 12*2bc61da9SChao Xie region. There are 4 places in SOC has clock control logic: 13*2bc61da9SChao Xie "mpmu", "apmu", "apbc", "apbcp". So four reg spaces need to be defined. 14*2bc61da9SChao Xie 15*2bc61da9SChao Xie- #clock-cells: should be 1. 16*2bc61da9SChao Xie- #reset-cells: should be 1. 17*2bc61da9SChao Xie 18*2bc61da9SChao XieEach clock is assigned an identifier and client nodes use this identifier 19*2bc61da9SChao Xieto specify the clock which they consume. 20*2bc61da9SChao Xie 21*2bc61da9SChao XieAll these identifier could be found in <dt-bindings/clock/marvell-pxa910.h>. 22